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參數(shù)資料
| 型號： | XPC750EC |
| 英文描述： | XPC750P/D XPC750P RISC Microprocessor Hardware Specifications |
| 中文描述： | XPC750P /數(shù)XPC750P RISC微處理器硬件規(guī)格 |
| 文件頁數(shù)： | 46/52頁 |
| 文件大?。?/td> | 1274K |
| 代理商： | XPC750EC |
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46
MPC755 RISC Microprocessor Hardware Specifications
MOTOROLA
Document Revision History
1.9
Document Revision History
Table 19 provides a revision history for this hardware specification.
Table 19. Document Revision History
Rev. No.
Substantive Change(s)
0
Product announced. Documentation made publicly available.
1
Corrected errors in Section 1.2.
Removed references to MPC745 CBGA package in Sections 1.3 and 1.4.
Added airflow values for
θ
JA
to Table 5.
Corrected V
IH
maximum for 1.8 V mode in Table 6.
Power consumption values added to Table 7.
Corrected t
MXRH
in Table 9, deleted Note 2 application note reference.
Added Max f
L2CLK
and Min t
L2CLK
values to Table 11.
Updated timing values in Table 12.
Corrected Note 2 of Table 13.
Changed Table 14 to reflect I/F voltages supported.
Removed 133 MHz and 150 MHz columns from Table 16.
Added document reference to Section 1.7.
Added DBB to list of signals requiring pull-ups in Section 1.8.7.
Removed log entries from Table 20 for revisions prior to public release.
2
1.8 V/2.0 V mode no longer supported; added 2.5 V support.
Removed 1.8 V/2.0 V mode data from Tables 2, 3, and 6.
Added 2.5 V mode data to Tables 2, 3, and 6.
Extended recommended operating voltage (down to 1.8 V) for V
DD
, AV
DD
, and L2AV
DD
for 300 MHz
and 350 MHz parts in Table 3.
Updated Table 7 and test conditions for power consumption specifications.
Corrected Note 6 of Table 9 to include TLBISYNC as a mode-select signal.
Updated AC timing specifications in Table 10.
Updated AC timing specifications in Table 12.
Corrected AC timing specifications in Table 13.
Added L1_TSTCLK, L2_TSTCLK, and LSSD_MODE pull-up requirements to Section 1.8.6.
Corrected Figure 22.
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