參數(shù)資料
型號(hào)： XPC750EC
英文描述： XPC750P/D XPC750P RISC Microprocessor Hardware Specifications
中文描述： XPC750P /數(shù)XPC750P RISC微處理器硬件規(guī)格
文件頁(yè)數(shù)： 6/52頁(yè)
文件大小： 1274K
代理商： XPC750EC
6
MPC755 RISC Microprocessor Hardware Specifications
MOTOROLA
Electrical and Thermal Characteristics
Packages
MPC745: Surface mount 255 plastic ball grid array (PBGA)
MPC755: Surface mount 360 ceramic ball grid array (CBGA)
Surface mount 360 plastic ball grid array (PBGA)
2.0 V ±100 mV DC (nominal; some parts support core voltages down
to 1.8 V; see Table 3 for recommended operating conditions)
2.5 V ±100 mV DC or
3.3 V ±165 mV DC (input thresholds are configuration pin selectable)
Core power supply
I/O power supply
1.4
Electrical and Thermal Characteristics
This section provides the AC and DC electrical specifications and thermal characteristics for the MPC755.
1.4.1
DC Electrical Characteristics
Table 1 to Table 7 describe the MPC755 DC electrical characteristics. Table 1 provides the absolute
maximum ratings.
Table 1. Absolute Maximum Ratings
1
Characteristic
Symbol
Maximum Value
Unit
Notes
Core supply voltage
V
DD
–0.3 to 2.5
V
4
PLL supply voltage
AV
DD
–0.3 to 2.5
V
4
L2 DLL supply voltage
L2AV
DD
–0.3 to 2.5
V
4
Processor bus supply voltage
OV
DD
–0.3 to 3.6
V
3
L2 bus supply voltage
L2OV
DD
–0.3 to 3.6
V
3
Input voltage
Processor bus
V
in
–0.3 to OV
DD
+ 0.3 V
V
2, 5
L2 bus
V
in
–0.3 to L2OV
DD
+ 0.3 V
V
2, 5
JTAG signals
V
in
–0.3 to 3.6
V
Storage temperature range
T
stg
–55 to 150
°C
Notes:
1. Functional and tested operating conditions are given in Table 3. Absolute maximum ratings are stress ratings
only, and functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device
reliability or cause permanent damage to the device.
2.
Caution:
Vin must not exceed OV
DD
or L2OV
DD
by more than 0.3 V at any time including during power-on reset.
3.
Caution:
L2OV
DD
/OV
DD
must not exceed V
DD
/AV
DD
/L2AV
DD
by more than 1.6 V during normal operation; this
limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences.
4.
Caution:
V
DD
/AV
DD
/L2AV
DD
must not exceed L2OV
DD
/OV
DD
by more than 0.4 V during normal operation; this
limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences.
5. V
in
may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 2.
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