2-10
Mindspeed Technologies
28229-DSH-001-B
CX2822x Hardware Description
CX28224/5/9 Data Sheet
JT
A
G
TRST*
Test Reset
E13
I/PU
When asserted, the internal boundary-scan logic is reset.
This pin has a pull-up resistor. Do not assert this reset
unless a clock is provided on TCK.
TCK
Test Clock
F13
I
Samples the value of TMS and TDI on its rising edge to
control the boundary scan operations.
TMS
Test Mode Select
E14
I/PU
Controls the boundary-scan Test Access Port (TAP)
controller operation. This pin has a pull-up resistor.
TDI
Test Data Input
F16
I/PU
The serial test data input. This pin has a pull-up resistor.
TDO
Test Data Output
F15
O
The serial test data output.
Te
st
TestEnable
T3
I
Factory test use only, tie to VSS.
TestMode
T4
I
Factory test use only, tie to VSS.
P
H
Y
Sid
e
Int
e
rfa
ce
PhyIntFcSel
PHY Interface Select
R4
I
If this pin is tied low, the PHY UTOPIA Interface mode is
selected. This table shows pin configurations with this pin
tied low.
If this pin is tied high, the PHY Serial mode is selected.
phyURxClk
UTOPIA Receive
Clock
R7
O
IMA_SysClk/2
phyURxEnb[0]*
PHY UTOPIA Receive
Enable
N8
O
Data transfer and output enable for Receive PHY cells
(active low). To support multiple PHY devices, separate
enable signals are provided. Depending on the software
configuration, some of the enable signals may not be
available and will be replaced by additional PHY cell bus
address bits. PhyURxEnb[1] is a No Connect on the
CX28224/5 devices.
phyURxEnb[1]*
P14
phyURxAddr[0]
PHY UTOPIA Receive
Address
T6
O
Receive PHY Cell Bus address. The following limitations
apply:
phyURxAddr[1]
T7
phyURxAddr[2]
P8
phyURxAddr[3]
T8
phyURxAddr[4]
R8
phyURxClAv[0]
PHY UTOPIA Receive
Cell Available
N9
I
Cell Available signals for Receive PHY interfaces.
phyURxClAv{n] is active when one or more complete cells
can be transferred. To support different PHY devices,
separate cell available signals are provided. This allows
expansion to 32 points. PhyURxClAv[1] is a No Connect on
the CX28224/5 devices.
phyURxClAv[1]
T16
I/PD
Table 2-3. CX2822x Pin Descriptions (5 of 12)
Pin Label
Signal Name
No.
I/O
Description
Device
Addresses
CX28224
0, 1, 31
CX28225
0–3, 31
CX28229
0–31