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| 型號(hào)： | 28229-14 |
| 廠商： | MINDSPEED TECHNOLOGIES INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | ATM/SONET/SDH SUPPORT CIRCUIT, PBGA256 |
| 封裝： | BGA-256 |
| 文件頁(yè)數(shù)： | 245/269頁(yè) |
| 文件大?。?/td> | 3376K |
| 代理商： | 28229-14 |
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28229-DSH-001-B
Mindspeed Technologies
4
-1
4
UTOPIA Interfaces
The CX2822x supports multi-PHY operation as described in the UTOPIA Level
specification (AF-PHY-0039.000, see www.atmforum.com). This standard allows up
to 31 ports to interface to one ATM layer device. The interface uses either 8-bit or 16-
bit wide data buses, and cell-level handshaking. The 16-bit mode, which can run at 50
MHz, supports data rates up to 800 Mbps. The Cx2822x implementation does not
support octet level handshaking or UTOPIA parity.
Each of the CX2822x's UTOPIA blocks has two sections, transmit and receive, each
of which has a 4-cell FIFO buffer. ATM cell data is placed in the transmit FIFOs
where it can then be passed to the ATM cell processing block. On the receive side of
the UTOPIA interface, incoming cells are placed in the receive FIFO until sent.
With regard to IMA, each IMA group is considered one logical port and will only take
up one UTOPIA address. For example, a group with 8 T1 links could be assigned to
address 0; the IMA engine handles the translation between the ATM layer and the
physical links. In addition, each pass-though connection also requires one address.
To provide maximum flexibility for system design the CX28229 has 3 UTOPIA Level
2 interfaces. This allows the CX28229 to be used in either UTOPIA-to-UTOPIA or
UTOPIA-to-Serial IMA applications or it can function as a stand-alone cell delineator
block. These interfaces are shown in Figure 4-1 and described below.
1.
IMA direct—This interface allows the ATM layer to interface directly to the IMA
engine. This would be the normal mode for all IMA applications. It is controlled
by registers in the IMA section.
2.
TC block direct—This interface is selected when the IMA engine is disabled and
the device is being used as a stand-alone cell delineator. It may also be invoked
during troubleshooting to verify serial port operation without having to run the
IMA drivers. It is configured by registers in the TC section.
3.
PHY side UTOPIA—This interface is selected when the TC block is disabled and
the designer wishes to interface to a device via an UTOPIA interface. This allows
the CX28229 IMA engine to address up to 32 ports on the line side.
NOTE:
By convention, data being transferred from the PHY to the ATM layer is
considered received data, while data from the ATM layer to the PHY is
called transmitted data.
相關(guān)PDF資料 |
PDF描述 |
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| 28230-13 | ATM SEGMENTATION AND REASSEMBLY DEVICE, PQFP208 |
| 28L0138-40R | 1 FUNCTIONS, FERRITE BEAD |
| 28L0138-70R | 1 FUNCTIONS, FERRITE BEAD |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 28-22916 | 制造商:CEBEK 功能描述:PRE ASSEMBLED MODULE BOARD PRECISION TIMER 15S-60MIN |
| 28-22918 | 制造商:CEBEK 功能描述:PRE ASSEMBLED MODULE BOARD PRECISION TIMER 0.1-10 SEC |
| 28-22920 | 制造商:CEBEK 功能描述:PRE ASSEMBLED MODULE BOARD PRECISION TIMER 1-99 SEC |
| 28-22922 | 制造商:CEBEK 功能描述:PRE ASSEMBLED MODULE BOARD SEQUENTIAL TIMER 1SEC-3MIN |
| 28-22926 | 制造商:CEBEK 功能描述:PRE ASSEMBLED MODULE BOARD ON DELAY TIMER 1-60 SECOND |
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