4-4
Mindspeed Technologies
28229-DSH-001-B
UTOPIA Interfaces
CX28224/5/9 Data Sheet
UTOPIA Receive Disable
The CX2822x has a UTOPIA receiver output disable feature which allows the user to
set up redundant or back-up PHYs with the same UTOPIA address on the same
UTOPIA bus. In this setup, both PHYs’ transmitters are enabled, sending out identical
data streams. Both PHYs’ receivers are enabled, but only one is transferring data to
the ATM device. The receiver output is disabled in the backup PHY by writing the
UtopRxDis, bit 5, in the UTOP2 register (0x0E) to a logical 1. This disable places five
of the backup PHY’s signals, URxData, URxPrty, URxSOC, URxClAv, and UTxClAv,
in a high-impedance state, preventing data and control signals from being passed to
the ATM layer device. The disabled receiver will flush its FIFOs at the same rate as
the enabled one, but all data it has received, except the last four cells, will be lost.
Should the primary PHY device encounter an unacceptable error rate, software can
quickly enable the backup PHY and disable the primary PHY, reducing cell loss in the
transition.
HEC Override
In normal operation, the HEC is calculated by the TC layer and put in byte 5, UDF1.
This may be overridden by setting bit 7 of the CGEN register (0x08) to a 1. In this
case, data inserted by the ATM layer into byte 5 is transmitted unchanged by the
device.
Table 4-1. Device Configuration Options
ATMMux [7,6]
(ATMINTFC, 0x202)
PhyIntFcSel
(Pin R4)
Description
01
Low
IMA UTOPIA using the PHY Side UTOPIA; UTOPIA-to-UTOPIA; TC block/serial
ports not used.
01
High
IMA UTOPIA using Internal TC block;
UTOPIA-to-Serial mode; 8 internal serial ports
10
High
TC only; Device used as Stand-alone cell delineator with 8 serial ports; IMA
block not used.