28229-DSH-001-B
Mindspeed Technologies
2
-19
CX28224/5/9 Data Sheet
CX2822x Hardware Description
Figure 2-4. CX28229 Logic Diagram (UTOPIA-to-Serial)
..
.
Memory Address Bus
Chip Enable
Output Enable
MemAddr[19:0]
MemCtrl_CE*
MemCtrl_OE*
MemCtrl_WE*
O Write Enable
External Memory
Memory Data Bus
MemData[15:0]
I/O
O
Interface
SRAM Clock
MemCtrl_Clk
MemCtrl_ADSC
O Address Enable
O
IMA Clocks
External Memory Select
ExtMemSel
I
ATM Transmit Address Bus
ATM Transmit Start Of Cell
ATM Transmit Parity
SPRxClk[0]
SPRxData[0]
SPRxSync[0]
Microprocessor Clock
Chip Select
Address Strobe, Write Control
Write/Read, Read Control
ATM Transmit Clock
Address Bus
ATM Transmit Enable
Sync/Async Mode Select
Microprocessor
I/O
MicroData[7:0]
Interface
I
MicroClk
MAS*, MWr*
MW/R, MRd*
MicroAddr[10:0]
Port 0
I
MSyncMode
I
Microprocessor Data Bus
Test Reset
Test Clock
Test Data Output
TDO
atmUTxAddr[4:0]
TRST*
TCK
O
One Second
I/O
ATM Receive Cell Available
ATM Receive Start of Cell
ATM Receive Parity
OneSecIO
atmURxClAv
atmURxSOC
atmURxPrty
atmUTxSOC
atmUTxPrty
ATM UTOPIA Transmit
atmURxData[15:0]
O ATM Receive Data Bus
atmUTxClk
atmUTxEnb*
atmUTxClAv
O
JTAG Interface
Test Mode Select
TMS
Test Data Input
TDI
ATM UTOPIA Receive
ATM Transmit Data Bus
atmUTxData[15:0]
I
ATM Receive Clock
atmURxClk
ATM Receive Enable
atmURxEnb*
ATM Receive Address Bus
atmURxAddr[4:0]
I
O
Line Interface
ATM Transmit Cell Available
MicroInt*
O Summary Interrupt
Interface
SPRxClk[7]
SPRxData[7]
SPRxSync[7]
I
SPTxClk[7]
SPTxData[7]
SPTxSync[7]
I/O
I
O
MRdy
Ready
SPTxClk[0]
SPTxData[0]
SPTxSync[0]
I/O
I
O
PhyIntFcSel (1)
8kHzIn
Reset
Reset*
I
One Second Input/Output
Transmit Clock
Transmit Data
Transmit Data Marker
Reset
PHY Interface Select
8kHzIn Clock
Receive Clock
Receive Data
MCS*
Receive Clock
Receive Data
Receive Data Marker
Transmit Clock
Transmit Data
Port 7
Line Interface
Interface
500027_003
Transmit Data Marker
Receive Data Marker
IMA System Clock
IMA_SysClk
IMA Reference Clock
IMA_RefClk
I
Test Enable
TestEnable
Test Mode
TestMode
I
StatOut[1:0]
O Status Output
TxTRL[1:0]
O Transmit Reference Clock
(1) Pulled High