
7-70
Mindspeed Technologies
28229-DSH-001-B
Registers
CX28224/5/9 Data Sheet
0x404—IMA_MISC_CONFIG (IMA Miscellaneous Control)
This register contains some of the basic IMA Subsystem configuration.
0x405—IMA_MEM_LOW_TEST (IMA Memory Test Address
(Bits 0–7))
Registers 0x405—0x408 are used to perform memory diagnostic tests on the internal
or external differential delay SRAM.
0x406—IMA_MEM_HI_TEST (IMA Memory Test Address
(Bits 8–15))
Bit
Default
Name
Description
7
——
Reserved. Set to 0
6
0
Alternate GTSM Mode
1 = When the GTSM is down, ATMUTxClAv for that group is controlled as if all
configured links in the group are Active.
0 = When the GTSM is down, ATMUTxClAv for that group is inactive.
5–4
0
PHY Size
This two bit field determines the use of the PHY side ClAv and En* signals
0 = ClAv and En* for every 4 PHY addresses (support 8 ports total)
1 = ClAv and En* for every 16 PHY addresses (support 32 ports total)
2 = ClAv and En* for all PHY addresses (support 32 ports total)
3 = ClAv and En* for every 8 PHY addresses (support 16 ports total)
3
0
Enable External HEC
Checker
1 = Bit 7 of the HEC Byte is a HEC error flag
0 = Use the HEC Error checker within the IMA block
2
0
Check ATMUTxAddr[4]
and ATMURxAddr[4]
0 = mask bits (don’t care)
1 = Check ATMUTxAddr[4] and TMURxAddr[4] for correct value
1
0
Check ATMUTxAddr[3]
and ATMURxAddr[3]
0 = mask bits (don’t care)
1 = Check ATMUTxAddr[3] and ATMURxAddr[3] for correct value
0
Check ATMUTxAddr[2]
and ATMURxAddr[2]
0 = mask bits (don’t care)
1 = Check ATMUTxAddr[2] and ATMURxAddr[2] for correct value
Bit
Default
Name
Description
7–0
0x00
Memory Test
Address
This field contains the least significant bits of the memory test address for the
selected memory component. Range: 0x00–0xFF
Bit
Default
Name
Description
7–0
0x00
Memory Test
Address
This field contains the middle significant bits of the memory test address for the
selected memory component. Range: 0x00–0xFF