28229-DSH-001-B
Mindspeed Technologies
7
-69
CX28224/5/9 Data Sheet
Registers
0x402—IMA_SUBSYS_CONFIG (IMA Configuration Control)
This register contains some of the basic IMA Subsystem configuration.
0x403—IMA_MISC_STATUS (IMA Miscellaneous Status)
This register contains miscellaneous status information for the IMA Subsystem.
Read-only.
Bit
Default
Name
Description
7–6
0
Link Type
Sets default link type for all IMA groups. Not used with variable rate facilities
0 = T1
1 = E1
2 = Alternate T1 (1.544 Mbps payload)
3 = Alternate E1 (1.984 Mbps payload)
5–4
0
SRAM size
0 = 25 ms (E1 mode)
1 = 50 ms
2 = 100 ms
3 = 200 ms
3
0
Number of SRAMs
0 = 1 SRAM, Set to 0 for all CX2822X devices
2–0
0
Number of Ports
This field indicates the range of valid PHY addresses.
0: addresses 0x00–0x03 are valid
1: addresses 0x00–0x07 are valid
2: addresses 0x00–0x0B are valid
3: addresses 0x00–0x0F are valid
4: addresses 0x00–0x13 are valid
5: addresses 0x00–0x17 are valid
6: addresses 0x00–0x1B are valid
7: addresses 0x00–0x1F are valid
This field has different ranges depending on Product type:
CX28224: Unused, Set to 0
CX28225: Unused, Set to 0
CX28229: Range: 0–7
Bit
Default
Name
Description
7
—
State of TxAddr[4]
This bit is the current state of the signal ATMUTxAddr[4].
6
—
State of RxAddr[4]
This bit is the current state of the signal ATMURxAddr[4].
5
——
Reserved
4
—
ATM Data Width
This bit indicates whether the ATM Utopia bus is operating in 16 bit (high) or 8 bit
(low) data mode.
3
—
IMA_RefClk Error
This bit is set high if a transition detector for IMA_RefClk detects a bad signal. This
bit is active high and is reset upon reading this address.
2
—
Tx ATM Parity Error
This bit indicates that a parity error has been detected on the Transmit ATM side
Utopia bus. This bit is active high and is reset upon reading this address.
1
——
Reserved.
0
—
Rx PHY Parity Error
This bit indicates that a parity error has been detected on the Receive PHY side cell
bus. This bit is active high and is reset upon reading this address.