參數(shù)資料
型號(hào)： ADUuC7027BSTZ62-RL
廠商： Analog Devices, Inc.
英文描述： Precision Analog Microcontroller 12-bit Analog I/O, ARM7TDMI MCU
中文描述： 精密模擬微控制器的12位模擬I / O，ARM7TDMI的微控制器
文件頁(yè)數(shù)： 21/92頁(yè)
文件大小： 850K
代理商： ADUUC7027BSTZ62-RL
ADuC7019/20/21/22/24/25/26/27
Table 11. Pin Function Descriptions (ADuC7024/ADuC7025 64-Lead CSP and ADuC7024/ADuC7025 64-Lead LQFP)
Pin No.
Mnemonic
Description
1
ADC4
Single-Ended or Differential Analog Input 4.
2
ADC5
Single-Ended or Differential Analog Input 5.
3
ADC6
Single-Ended or Differential Analog Input 6.
4
ADC7
Single-Ended or Differential Analog Input 7.
5
ADC8
Single-Ended or Differential Analog Input 8.
6
ADC9
Single-Ended or Differential Analog Input 9.
7
GND
REF
Ground Voltage Reference for the ADC. For optimal performance, the analog power supply
should be separated from IOGND and DGND.
8
ADCNEG
Bias Point or Negative Analog Input of the ADC in Pseudo Differential Mode. Must be connected
to the ground of the signal to convert. This bias point must be between 0 V and 1 V.
9
DAC0/ADC12
DAC0 Voltage Output/Single-Ended or Differential Analog Input 12. DAC outputs are not
present on the ADuC7025.
10
DAC1/ADC13
DAC1 Voltage Output/Single-Ended or Differential Analog Input 13. DAC outputs are not
present on the ADuC7025.
11
TMS
JTAG Test Port Input, Test Mode Select. Debug and download access.
12
TDI
JTAG Test Port Input, Test Data In. Debug and download access
13
P4.6/PLAO[14]
General-Purpose Input and Output Port 4.6/Programmable Logic Array Output Element 14.
14
P4.7/PLAO[15]
General-Purpose Input and Output Port 4.7/Programmable Logic Array Output Element 15.
15
BM/P0.0/CMP
OUT
/PLAI[7]
Multifunction I/O Pin. Boot mode. The ADuC7024/ADuC7025 enter download mode if BM is low at
reset and executes code if BM is pulled high at reset through a 1 k
resistor/General-Purpose Input
and Output Port 0.0/Voltage Comparator Output/Programmable Logic Array Input Element 7.
16
P0.6/T1/MRST/PLAO[3]
Multifunction Pin, Driven Low After Reset. General-Purpose Output Port 0.6/Timer1
Input/Power-On Reset Output/Programmable Logic Array Output Element 3.
17
TCK
JTAG Test Port Input, Test Clock. Debug and download access.
18
TDO
JTAG Test Port Output, Test Data Out. Debug and download access.
19
IOGND
Ground for GPIO. Typically connected to DGND.
20
IOV
DD
3.3 V Supply for GPIO and Input of the On-Chip Voltage Regulator.
21
LV
DD
2.6 V Output of the On-Chip Voltage Regulator. This output must be connected to a 0.47 μF
capacitor to DGND only.
22
DGND
Ground for Core Logic.
23
P3.0/PWM0
H
/PLAI[8]
General-Purpose Input and Output Port 3.0/PWM Phase 0 High-Side Output/Programmable
Logic Array Input Element 8.
24
P3.1/PWM0
L
/PLAI[9]
General-Purpose Input and Output Port 3.1/PWM Phase 0 Low-Side Output/Programmable
Logic Array Input Element 9.
25
P3.2/PWM1
H
/PLAI[10]
General-Purpose Input and Output Port 3.2/PWM Phase 1 High-Side Output/Programmable
Logic Array Input Element 10.
26
P3.3/PWM1
L
/PLAI[11]
General-Purpose Input and Output Port 3.3/PWM Phase 1 Low-Side Output/Programmable
Logic Array Input Element 11.
27
P0.3/TRST/ADC
BUSY
General-Purpose Input and Output Port 0.3/JTAG Test Port Input, Test Reset/ADC
BUSY
Signal
Output.
28
RST
Reset Input, Active Low.
29
P3.4/PWM2
H
/PLAI[12]
General-Purpose Input and Output Port 3.4/PWM Phase 2 High-Side Output/Programmable
Logic Array Input 12.
30
P3.5/PWM2
L
/PLAI[13]
General-Purpose Input and Output Port 3.5/PWM Phase 2 Low-Side Output/Programmable
Logic Array Input Element 13.
31
IRQ0/P0.4/PWM
TRIP
/PLAO[1]
Multifunction I/O Pin. External Interrupt Request 0, Active High/General-Purpose Input and
Output Port 0.4/PWM Trip External Input/Programmable Logic Array Output Element 1.
32
IRQ1/P0.5/ADC
BUSY
/PLAO[2]
Multifunction I/O Pin. External Interrupt Request 1, Active High/General-Purpose Input and
Output Port 0.5/ADC
BUSY
Signal Output/Programmable Logic Array Output Element 2.
33
P2.0/SPM9/PLAO[5]/CONV
START
Serial Port Multiplexed. General-Purpose Input and Output Port 2.0/UART/Programmable Logic
Array Output Element 5/Start Conversion Input Signal for ADC.
34
P0.7/ECLK/XCLK/SPM8/PLAO[4]
Serial Port Multiplexed. General-Purpose Input and Output Port 0.7/Output for External Clock
Signal/Input to the Internal Clock Generator Circuits/UART/Programmable Logic Array Output
Element 4.
35
XCLKO
Output from the Crystal Oscillator Inverter.
Rev. A | Page 21 of 92
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