參數(shù)資料
型號(hào)： ADUuC7027BSTZ62-RL
廠商： Analog Devices, Inc.
英文描述： Precision Analog Microcontroller 12-bit Analog I/O, ARM7TDMI MCU
中文描述： 精密模擬微控制器的12位模擬I / O，ARM7TDMI的微控制器
文件頁數(shù)： 68/92頁
文件大?。?/td> 850K
代理商： ADUUC7027BSTZ62-RL
ADuC7019/20/21/22/24/25/26/27
I
2
C Registers
The I
2
C peripheral interface consists of 18 MMRs, which are
discussed in this section.
Rev. A | Page 68 of 92
I2CxMSTA Registers
Name
I2C0MSTA
I2C1MSTA
Address
0xFFFF0800
0xFFFF0900
Default Value
0x00
0x00
Access
R
R
I2CxMSTA are status registers for the master channel.
Table 60. I2C0MSTA MMR Bit Descriptions
Bit
Description
7
Master Transmit FIFO Flush.
Set
by user to flush the master
Tx FIFO.
Cleared
automatically once the master Tx FIFO is
flushed. This bit also flushes the slave receive FIFO.
6
Master Busy.
Set
automatically if the master is busy.
Cleared
automatically.
5
Arbitration Loss.
Set
in multimaster mode if another master
has the bus.
Cleared
when the bus becomes available.
4
No ACK.
Set
automatically if there is no acknowledge of the
address by the slave device.
Cleared
automatically by
reading the I2C0MSTA register.
3
Master Receive IRQ.
Set
after receiving data.
Cleared
automatically by reading the I2C0MRX register.
2
Master Transmit IRQ.
Set
at the end of a transmission.
Cleared
automatically by writing to the I2C0MTX register.
1
Master Transmit FIFO Underflow.
Set
automatically if the
master transmit FIFO is underflowing.
Cleared
automatically by writing to the I2C0MTX register.
0
Master TX FIFO Empty.
Set
automatically if the master
transmit FIFO is empty.
Cleared
automatically by writing to
the I2C0MTX register.
I2CxSSTA Registers
Name
Address
I2C0SSTA
0xFFFF0804
I2C1SSTA
0xFFFF0904
Default Value
0x01
0x01
Access
R
R
I2CxSSTA are status registers for the slave channel.
Table 61. I2C0SSTA MMR Bit Descriptions
Bit
Value
Description
31:15
Reserved. These bits should be written as 0.
14
START Decode Bit.
Set
by hardware if the
device receives a valid START + matching
address.
Cleared
by an I
2
C STOP condition
or an I
2
C general call reset.
13
Repeated START Decode Bit.
Set
by hardware
if the device receives a valid repeated START +
matching address.
Cleared
by an I
2
C STOP
condition, a read of the I2CSSTA register,
or an I
2
C general call reset.
12:11
ID Decode Bits.
00
Received Address Natched ID Register 0.
01
Received Address Matched ID Register 1.
10
Received Address Matched ID Register 2.
11
Received Address Matched ID Register 3.
10
Stop After Start and Matching Address
Interrupt.
Set
by hardware if the slave device
receives an I
2
C STOP condition after a previous
I
2
C START condition and matching address.
Cleared
by a read of the I2C0SSTA register.
9:8
General Call ID.
00
No General Call.
01
General Call Reset and Program Address.
10
General Call Program Address.
11
General Call Matching Alternative ID.
7
General Call Interrupt.
Set
if the slave device
receives a general call of any type. C
leared
by
setting Bit 8 of the I2CxCFG register. If it is a
general call reset, then all registers are at their
default values. If it is a hardware general call,
then the Rx FIFO holds the second byte of the
general call. This is similar to the I2C0ALT
register (unless it is a general call to reprogram
the device address). For more details, see I
2
C
bus specification, version 2.1, Jan. 2000.
6
Slave Busy.
Set
automatically if the slave is
busy.
Cleared
automatically.
5
No ACK.
Set
if master asking for data and no
data is available.
Cleared
automatically by
reading the I2C0SSTA register.
4
Slave Receive FIFO Overflow.
Set
automatically
if the slave receive FIFO is overflowing.
Cleared
automatically by reading the I2C0SSTA register.
3
Slave Receive IRQ.
Set
after receiving data.
Cleared
automatically by reading the I2C0SRX
register or flushing the FIFO.
2
Slave Transmit IRQ.
Set
at the end of a trans-
mission.
Cleared
automatically by writing to
the I2C0STX register.
1
Slave Transmit FIFO Underflow.
Set
automatically
if the slave transmit FIFO is underflowing.
Cleared
automatically by writing to the
I2C0SSTA MMR.
0
Slave Transmit FIFO Empty.
Set
automatically if
the slave transmit FIFO is empty.
Cleared
automatically by writing to the I2C0STX register.
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