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| 型號： | ADUuC7027BSTZ62-RL |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Precision Analog Microcontroller 12-bit Analog I/O, ARM7TDMI MCU |
| 中文描述： | 精密模擬微控制器的12位模擬I / O，ARM7TDMI的微控制器 |
| 文件頁數(shù)： | 49/92頁 |
| 文件大?。?/td> | 850K |
| 代理商： | ADUUC7027BSTZ62-RL |
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ADuC7019/20/21/22/24/25/26/27
Linearity degradation near ground and V
DD
is caused by
saturation of the output amplifier, and a general representation
of its effects (neglecting offset and gain error) is illustrated in
Figure 52. The dotted line in Figure 52 indicates the ideal transfer
function, and the solid line represents what the transfer function
might look like with endpoint nonlinearities due to saturation of
the output amplifier. Note that Figure 52 represents a transfer
function in 0-to-AV
DD
mode only. In 0-to-V
REF
or 0-to-DAC
REF
modes (with V
REF
< AV
DD
or DAC
REF
< AV
DD
), the lower non-
linearity is similar. However, the upper portion of the transfer
function follows the “ideal” line right to the end (V
REF
in this case,
not AV
DD
), showing no signs of endpoint linearity errors.
Rev. A | Page 49 of 92
0
AV
DD
AV
DD
– 100mV
100mV
0x00000000
0x0FFF0000
Figure 52. Endpoint Nonlinearities Due to Amplifier Saturation
The endpoint nonlinearities conceptually illustrated in
Figure 52 get worse as a function of output loading. Most of
the ADuC7019/7020/7021/7022/7024/7025/7026/7027’s data
sheet specifications assume a 5 k
Ω
resistive load to ground at
the DAC output. As the output is forced to source or sink more
current, the nonlinear regions at the top or bottom
(respectively) of Figure 52 become larger. With larger current
demands, this can significantly limit output voltage swing.
POWER SUPPLY MONITOR
The power supply monitor regulates the IOV
DD
supply on the
ADuC7019/7020/7021/7022/7024/7025/7026/7027. It indicates
when the IOV
DD
supply pin drops below one of two supply trip
points. The monitor function is controlled via the PSMCON
register. If enabled in the IRQEN or FIQEN register, then the
monitor interrupts the core using the PSMI bit in the PSMCON
MMR. This bit is immediately cleared once CMP goes high.
This monitor function allows the user to save working registers
to avoid possible data loss due to the low supply or brown-out
conditions. It also ensures that normal code execution does not
resume until a safe supply level has been established.
PSMCON Register
Name
PSMCON
Address
0xFFFF0440
Default Value
0x0008
Access
R/W
Table 28. PSMCON MMR Bit Descriptions
Bit
Name
Description
3
CMP
Comparator Bit. This is a read-only bit and
directly reflects the state of the comparator.
Read 1 indicates that the IOV
DD
supply is above
its selected trip point or the PSM is in power-
down mode. Read 0 indicates the IOV
DD
supply is
below its selected trip point. This bit should be
set before leaving the interrupt service routine.
2
TP
Trip Point Selection Bits. 0 = 2.79 V, 1 = 3.07 V.
1
PSMEN
Power Supply Monitor Enable Bit.
Set
to 1 to
enable the power supply monitor circuit.
Clear
to
0 to disable the power supply monitor circuit.
0
PSMI
Power Supply Monitor Interrupt Bit. This bit is set
high by the MicroConverter once when CMP
goes low, indicating low I/O supply. The PSMI bit
can be used to interrupt the processor. Once
CMP returns high, the PSMI bit can be cleared by
writing a 1 to this location. A 0 write has no
effect. There is no timeout delay; PSMI can be
immediately cleared once CMP goes high.
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