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| 型號(hào)： | ADUuC7027BSTZ62-RL |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Precision Analog Microcontroller 12-bit Analog I/O, ARM7TDMI MCU |
| 中文描述： | 精密模擬微控制器的12位模擬I / O，ARM7TDMI的微控制器 |
| 文件頁數(shù)： | 31/92頁 |
| 文件大?。?/td> | 850K |
| 代理商： | ADUUC7027BSTZ62-RL |
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ADuC7019/20/21/22/24/25/26/27
OVERVIEW OF THE ARM7TDMI CORE
The ARM7 core is a 32-bit reduced instruction set computer
(RISC). It uses a single 32-bit bus for instruction and data. The
length of the data can be 8 bits, 16 bits, or 32 bits. The length of
the instruction word is 32 bits.
Rev. A | Page 31 of 92
The ARM7TDMI is an ARM7 core with four additional
features:
T support for the thumb (16 bit) instruction set
D support for debug
M support for long multiplications
I includes the embeddedICE module to support embedded
system debugging
THUMB MODE (T)
An ARM instruction is 32 bits long. The ARM7TDMI processor
supports a second instruction set that has been compressed
into 16 bits, called the thumb instruction set. Faster execution
from 16-bit memory and greater code density can usually be
achieved by using the thumb instruction set instead of the ARM
instruction set, which makes the ARM7TDMI core particularly
suitable for embedded applications.
However, the thumb mode has two limitations:
Thumb code usually uses more instructions for the same
job. As a result, ARM code is usually best for maximizing
the performance of the time-critical code.
The thumb instruction set does not include some of the
instructions needed for exception handling, which
automatically switches the core to ARM code for exception
handling.
See the ARM7TDMI user guide for details on the core
architecture, the programming model, and both the ARM and
ARM thumb instruction sets.
LONG MULTIPLY (M)
The ARM7TDMI instruction set includes four extra instruc-
tions that perform 32-bit by 32-bit multiplication with 64-bit
result, and 32-bit by 32-bit multiplication-accumulation (MAC)
with 64-bit result. These results are achieved in fewer cycles
than required on a standard ARM7 core.
EMBEDDEDICE (I)
EmbeddedICE provides integrated on-chip support for the core.
The EmbeddedICE module contains the breakpoint and
watchpoint registers that allow code to be halted for debugging
purposes. These registers are controlled through the JTAG test port.
When a breakpoint or watchpoint is encountered, the
processor halts and enters debug state. Once in a debug
state, the processor registers can be inspected as well as the
Flash/EE, the SRAM, and the memory mapped registers.
EXCEPTIONS
ARM supports five types of exceptions and a privileged
processing mode for each type. The five types of exceptions are:
Normal interrupt or IRQ. This is provided to service
general-purpose interrupt handling of internal and
external events.
Fast interrupt or FIQ. This is provided to service data
transfer or communication channel with low latency. FIQ
has priority over IRQ.
Memory abort.
Attempted execution of an undefined instruction.
Software interrupt instruction (SWI). This can be used to
make a call to an operating system.
Typically, the programmer defines interrupt as IRQ, but for
higher priority interrupt, that is, faster response time, the
programmer can define interrupt as FIQ.
ARM REGISTERS
ARM7TDMI has a total of 37 registers: 31 general-purpose
registers and six status registers. Each operating mode has
dedicated banked registers.
When writing user-level programs, 15 general-purpose 32-bit
registers (R0 to R14), the program counter (R15) and the
current program status register (CPSR) are usable. The
remaining registers are only used for system-level programming
and for exception handling.
When an exception occurs, some of the standard registers are
replaced with registers specific to the exception mode. All
exception modes have replacement banked registers for the stack
pointer (R13) and the link register (R14) as represented in
Figure
32. The fast interrupt mode has more registers (R8 to R12) for
fast interrupt processing. This means the interrupt processing can
begin without the need to save or restore these registers, and thus
save critical time in the interrupt handling process.
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