參數(shù)資料
型號(hào)： ADUuC7027BSTZ62-RL
廠商： Analog Devices, Inc.
英文描述： Precision Analog Microcontroller 12-bit Analog I/O, ARM7TDMI MCU
中文描述： 精密模擬微控制器的12位模擬I / O，ARM7TDMI的微控制器
文件頁數(shù)： 63/92頁
文件大小： 850K
代理商： ADUUC7027BSTZ62-RL
ADuC7019/20/21/22/24/25/26/27
Error = 0% compared to 6.25% with the normal baud rate
generator.
Rev. A | Page 63 of 92
UART Registers Definition
The UART interface consists on 12 registers: COMTX,
COMRX, COMDIV0, COMIEN0, COMDIV1, COMIIDO,
COMCON0, COMCON1, COMSTA0, COMSTA1, COMSCR,
and COMDIV2.
COMTX Register
Name
COMTX
Address
0xFFFF0700
Default Value
0x00
Access
R/W
COMTX is an 8-bit transmit register.
COMRX Register
Name
COMRX
Address
0xFFFF0700
Default Value
0x00
Access
R
COMRX is an 8-bit receive register.
COMDIV0 Register
Name
COMDIV0
Address
0xFFFF0700
Default Value
0x00
Access
R/W
COMDIV0 is a low-byte divisor latch. COMTX, COMRX,
and COMDIV0 share the same address location. COMTX
and COMRX can be accessed when Bit 7 in COMCON0
register is cleared. COMDIV0 can be accessed when Bit 7
of COMCON0 is set.
COMIEN0 Register
Name
COMIEN0
Address
0xFFFF0704
Default Value
0x00
Access
R/W
COMIEN0 is the interrupt enable register.
Table 48. COMIEN0 MMR Bit Descriptions
Bit
Name
Description
7:4
Reserved.
3
EDSSI
Modem Status Interrupt Enable Bit.
Set
by
user to enable generation of an interrupt if
any of COMSTA1[3:0] are set.
Cleared
by user.
2
ELSI
Rx Status Interrupt Enable Bit.
Set
by user to
enable generation of an interrupt if any of
COMSTA0[3:0] are set.
Cleared
by user.
1
ETBEI
Enable Transmit Buffer Empty Interrupt.
Set
by user to enable interrupt when buffer is
empty during a transmission.
Cleared
by user.
0
ERBFI
Enable Receive Buffer Full Interrupt.
Set
by
user to enable interrupt when buffer is full
during a reception.
Cleared
by user.
COMDIV1 Register
Name
COMDIV1
Address
0xFFFF0704
Default Value
0x00
Access
R/W
COMDIV1 is a divisor latch (high byte) register.
COMIID0 Register
Name
COMIID0
Address
0xFFFF0708
Default Value
0x01
Access
R
COMIID0 is the interrupt identification register.
Table 49. COMIID0 MMR Bit Descriptions
Bit 2:1
Status
Bits
NINT
Priority
00
1
11
0
1
Bit 0
Definition
No interrupt
Receive line
status interrupt
Receive buffer
full interrupt
Transmit buffer
empty interrupt
Clearing
Operation
Read COMSTA0
10
0
2
Read COMRX
01
0
3
Write data to
COMTX or read
COMIID0
Read COMSTA1
register
00
0
4
Modem status
interrupt
COMCON0 Register
Name
COMCON0
Address
0xFFFF070C
Default Value
0x00
Access
R/W
COMCON0 is the line control register.
Table 50. COMCON0 MMR Bit Descriptions
Bit
Name
Description
7
DLAB
Divisor Latch Access.
Set
by user to enable
access to COMDIV0 and COMDIV1 registers.
Cleared
by user to disable access to COMDIV0
and COMDIV1 and enable access to COMRX
and COMTX.
6
BRK
Set Break.
Set
by user to force SOUT to 0.
Cleared
to operate in normal mode.
5
SP
Stick Parity.
Set
by user to force parity to
defined values: 1 if EPS = 1 and PEN = 1,
0 if EPS = 0 and PEN = 1.
4
EPS
Even Parity Select Bit.
Set
for even parity.
Cleared
for odd parity.
3
PEN
Parity Enable Bit.
Set
by user to transmit and
check the parity bit.
Cleared
by user for no
parity transmission or checking.
2
STOP
Stop Bit.
Set
by user to transmit 1.5 stop bits if the
word length is 5 bits or 2 stop bits if the word
length is 6 bits, 7 bits, or 8 bits. The receiver
checks the first stop bit only, regardless of the
number of stop bits selected.
Cleared
by user to
generate 1 stop bit in the transmitted data.
1:0
WLS
Word Length Select:
00 = 5 bits, 01 = 6 bits
10 = 7 bits, 11 = 8 bits
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