參數(shù)資料
型號(hào)： ADUuC7027BSTZ62-RL
廠商： Analog Devices, Inc.
英文描述： Precision Analog Microcontroller 12-bit Analog I/O, ARM7TDMI MCU
中文描述： 精密模擬微控制器的12位模擬I / O，ARM7TDMI的微控制器
文件頁(yè)數(shù)： 24/92頁(yè)
文件大?。?/td> 850K
代理商： ADUUC7027BSTZ62-RL
ADuC7019/20/21/22/24/25/26/27
Pin No.
14
15
16
Rev. A | Page 24 of 92
Mnemonic
TMS
TDI
P0.1/PWM2
H
/BLE
Description
JTAG Test Port Input, Test Mode Select. Debug and download access.
JTAG Test Port Input, Test Data In. Debug and download access.
General-Purpose Input and Output Port 0.1/PWM Phase 2 High-Side Output/External Memory
Byte Low Enable.
General-Purpose Input and Output Port 2.3/External Memory Access Enable.
General-Purpose Input and Output Port 4.6/External Memory Interface/Programmable Logic
Array Output Element 14.
General-Purpose Input and Output Port 4.7/External Memory Interface/Programmable Logic
Array Output Element 15.
Multifunction I/O Pin. Boot Mode. The ADuC7026/ADuC7027 enter UART download mode if
BM is low at reset and execute code if BM is pulled high at reset through a 1 kΩ resistor/
General-Purpose Input and Output Port 0.0/Voltage Comparator Output/Programmable Logic
Array Input Element 7/External Memory Select 2.
Multifunction Pin, Driven Low After Reset. General-Purpose Output Port 0.6/Timer1
Input/Power-On Reset Output/Programmable Logic Array Output Element 3.
JTAG Test Port Input, Test Clock. Debug and download access.
JTAG Test Port Output, Test Data Out. Debug and download access.
General-Purpose Input and Output Port 0.2/PWM Phase 2 Low-Side Output/External Memory
Byte High Enable.
Ground for GPIO. Typically connected to DGND.
3.3 V Supply for GPIO and Input of the On-Chip Voltage Regulator.
2.6 V Output of the On-Chip Voltage Regulator. This output must be connected to a 0.47 μF
capacitor to DGND only.
Ground for Core Logic.
General-Purpose Input and Output Port 3.0/External Memory Interface/PWM Phase 0 High-
Side Output/Programmable Logic Array Input Element 8.
General-Purpose Input and Output Port 3.1/External Memory Interface/PWM Phase 0 Low-
Side Output/Programmable Logic Array Input Element 9.
General-Purpose Input and Output Port 3.2/External Memory Interface/PWM Phase 1 High-
Side Output/Programmable Logic Array Input Element 10.
General-Purpose Input and Output Port 3.3/External Memory Interface/PWM Phase 1 Low-
Side Output/Programmable Logic Array Input Element 11.
General-Purpose Input and Output Port 2.4/PWM Phase 0 High-Side Output/External Memory
Select 0.
General-Purpose Input and Output Port 0.3/JTAG Test Port Input, Test Reset/ADC
BUSY
Signal
Output.
General-Purpose Input and Output Port 2.5/PWM Phase 0 Low-Side Output/External Memory
Select 1.
General-Purpose Input and Output Port 2.6/PWM Phase 1 High-Side Output/External Memory
Select 2.
Reset Input, Active Low.
General-Purpose Input and Output Port 3.4/External Memory Interface/PWM Phase 2 High-
Side Output/Programmable Logic Array Input 12.
General-Purpose Input and Output Port 3.5/External Memory Interface/PWM Phase 2 Low-
Side Output/Programmable Logic Array Input Element 13.
Multifunction I/O Pin. External Interrupt Request 0, Active High/General-Purpose Input and
Output Port 0.4/PWM Trip External Input/Programmable Logic Array Output Element
1/External Memory Select 1.
Multifunction I/O Pin. External Interrupt Request 1, Active High/General-Purpose Input and
Output Port 0.5/ADC
BUSY
Signal Output/Programmable Logic Array Output Element 2/External
Memory Select 0.
Serial Port Multiplexed. General-Purpose Input and Output Port 2.0/UART/Programmable Logic
Array Output Element 5/Start Conversion Input Signal for ADC.
17
18
P2.3/AE
P4.6/AD14/PLAO[14]
19
P4.7/AD15/PLAO[15]
20
BM/P0.0/CMP
OUT
/PLAI[7]/MS2
21
P0.6/T1/MRST/PLAO[3]/AE
22
23
24
TCK
TDO
P0.2/ PWM2
L
/BHE
25
26
27
IOGND
IOV
DD
LV
DD
28
29
DGND
P3.0/AD0/PWM0
H
/PLAI[8]
30
P3.1/AD1/PWM0
L
/PLAI[9]
31
P3.2/AD2/PWM1
H
/PLAI[10]
32
P3.3/AD3/PWM1
L
/PLAI[11]
33
P2.4/PWM0
H
/MS0
34
P0.3/TRST/A16/ADC
BUSY
35
P2.5/PWM0
L
/MS1
36
P2.6/PWM1
H
/MS2
37
38
RST
P3.4/AD4/PWM2
H
/PLAI[12]
39
P3.5/AD5/PWM2
L
/PLAI[13]
40
IRQ0/P0.4/PWM
TRIP
/PLAO[1]/MS1
41
IRQ1/P0.5/ADC
BUSY
/PLAO[2]/MS0
42
P2.0/SPM9/PLAO[5]/CONV
START
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