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| 型號： | ADUuC7027BSTZ62-RL |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Precision Analog Microcontroller 12-bit Analog I/O, ARM7TDMI MCU |
| 中文描述： | 精密模擬微控制器的12位模擬I / O，ARM7TDMI的微控制器 |
| 文件頁數(shù)： | 67/92頁 |
| 文件大小： | 850K |
| 代理商： | ADUUC7027BSTZ62-RL |
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ADuC7019/20/21/22/24/25/26/27
Table 59. SPICON MMR Bit Descriptions
Bit
Description
15:13
Reserved.
12
Continuous Transfer Enable.
Set
by user to enable continuous transfer. In master mode, the transfer continues until no valid data
is available in the TX register. CS is asserted and remains asserted for the duration of each 8-bit serial transfer until TX is empty.
Cleared
by user to disable continuous transfer. Each transfer consists of a single 8-bit serial transfer. If valid data exists in the
SPITX register, then a new transfer is initiated after a stall period.
11
Loop Back Enable.
Set
by user to connect MISO to MOSI and test software.
Cleared
by user to be in normal mode.
10
Slave Output Enable.
Set
by user to enable the slave output.
Cleared
by user to disable slave output.
9
Slave Select Input Enable.
Set
by user in master mode to enable the output.
Cleared
by user to disable master output.
8
SPIRX Overflow Overwrite Enable.
Set
by user, the valid data in the RX register is overwritten by the new serial byte received.
Cleared
by user, the new serial byte received is discarded.
7
SPITX Underflow Mode.
Set
by user to transmit 0.
Cleared
by user to transmit the previous data.
6
Transfer and Interrupt Mode.
Set
by user to initiate transfer with a write to the SPITX register. Interrupt only occurs when TX is
empty.
Cleared
by user to initiate transfer with a read of the SPIRX register. Interrupt only occurs when RX is full.
5
LSB First Transfer Enable Bit.
Se
t by user, the LSB is transmitted first.
Cleared
by user, the MSB is transmitted first.
4
Reserved.
3
Serial Clock Polarity Mode Bit.
Set
by user, the serial clock idles high.
Cleared
by user, the serial clock idles low.
2
Serial Clock Phase Mode Bit.
Set
by user, the serial clock pulses at the beginning of each serial bit transfer.
Cleared
by user, the
serial clock pulses at the end of each serial bit transfer.
1
Master Mode Enable Bit.
Set
by user to enable master mode.
Cleared
by user to enable slave mode.
0
SPI Enable Bit.
Set
by user to enable the SPI.
Cleared
by user to disable the SPI.
Rev. A | Page 67 of 92
I
2
C COMPATIBLE INTERFACES
The ADuC7019/7020/7021/7022/7024/7025/7026/7027 support
two fully licensed I
2
C interfaces. The I
2
C interfaces are both
implemented as a full hardware master and slave interface. Because
the two I
2
C interfaces are identical, this data sheet describes only
I2C0 in detail. Note that the two masters and one of the slaves have
individual interrupts. See the Interrupt System section.
The two pins used for data transfer, SDA and SCL, are
configured in a wired-AND format that allows arbitration in a
multimaster system.
The I
2
C bus peripheral’s address in the I
2
C bus system is
programmed by the user. This ID can be modified any time a
transfer is not in progress. The user can configure the interface
to respond to four slave addresses.
The transfer sequence of an I
2
C system consists of a master
device initiating a transfer by generating a start condition while
the bus is idle. The master transmits the address of the slave
device and the direction of the data transfer in the initial
address transfer. If the master does not lose arbitration and the
slave acknowledges, then the data transfer is initiated. This
continues until the master issues a stop condition and the bus
becomes idle.
The I
2
C peripheral master and slave functionality are
independent and can be simultaneously active. A slave is
activated when a transfer has been initiated on the bus. If it is
not addressed, it remains inactive until another transfer is
initiated. This also allows a master device, which loses
arbitration, to respond as a slave in the same cycle.
Serial Clock Generation
The I
2
C master in the system generates the serial clock for a
transfer. The master channel can be configured to operate in
fast mode (400 kHz) or standard mode (100 kHz).
The bit rate is defined in the I2C0DIV MMR as follows:
f
f
k
serialcloc
+
)
(2
+
2
DIVL
DIVH
UCLK
+
=
where:
f
UCLK
= clock before the clock divider.
DIVH
= the high period of the clock.
DIVL
= the low period of the clock.
Thus, for 100 kHz operation,
DIVH
=
DIVL
= 0×CF
and for 400 kHz,
DIVH
=
DIVL
= 0×32
The I2C×DIV register corresponds to DIVH:DIVL.
Slave Addresses
The registers I2C0ID0, I2C0ID1, I2C0ID2, and I2C0ID3
contain the device IDs. The device compares the four I2C0IDx
registers to the address byte. The seven most significant bits of
either ID register must be identical to that of the seven most
significant bits of the first address byte received to be correctly
addressed. The LSB of the ID registers, the transfer direction
bit, is ignored in the process of address recognition.
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