參數(shù)資料
型號(hào)： ADUuC7027BSTZ62-RL
廠商： Analog Devices, Inc.
英文描述： Precision Analog Microcontroller 12-bit Analog I/O, ARM7TDMI MCU
中文描述： 精密模擬微控制器的12位模擬I / O，ARM7TDMI的微控制器
文件頁(yè)數(shù)： 84/92頁(yè)
文件大?。?/td> 850K
代理商： ADUUC7027BSTZ62-RL
ADuC7019/20/21/22/24/25/26/27
GROUNDING AND BOARD LAYOUT
RECOMMENDATIONS
As with all high resolution data converters, special attention
must be paid to grounding and PC board layout of
ADuC7019/7020/7021/7022/7024/7025/7026/7027-based
designs in order to achieve optimum performance from the
ADCs and DAC.
Rev. A | Page 84 of 92
Although the ADuC7019/7020/7021/7022/7024/7025/7026/7027
have separate pins for analog and digital ground (AGND and
IOGND), the user must not tie these to two separate ground
planes unless the two ground planes are connected very close to
the part. This is illustrated in the simplified example shown in
Figure 76a. In systems where digital and analog ground planes
are connected together somewhere else (at the system’s power
supply, for example), the planes cannot be reconnected near the
part, because a ground loop would result. In these cases, tie all the
ADuC7019/7020/7021/7022/7024/7025/7026/7027’s AGND and
IOGND pins to the analog ground plane, as illustrated in Figure
76b. In systems with only one ground plane, ensure that the
digital and analog components are physically separated onto
separate halves of the board so that digital return currents do not
flow near analog circuitry and vice versa. The ADuC7019/7020/
7021/7022/7024/7025/7026/7027 can then be placed between the
digital and analog sections, as illustrated in Figure 76c.
0
a.
PLACE ANALOG
COMPONENTS HERE
PLACE DIGITAL
COMPONENTS HERE
AGND
DGND
b.
PLACE ANALOG
COMPONENTS
HERE
PLACE DIGITAL
COMPONENTS HERE
AGND
DGND
c.
PLACE ANALOG
COMPONENTS HERE
PLACE DIGITAL
COMPONENTS HERE
DGND
Figure 76. System Grounding Schemes
In all of these scenarios, and in more complicated real-life
applications, pay particular attention to the flow of current from
the supplies and back to ground. Make sure the return paths for
all currents are as close as possible to the paths the currents
took to reach their destinations.
For example, do not power components on the analog side, as
seen in Figure 76b, with IOV
DD
because that would force return
currents from IOV
DD
to flow through AGND. Also, avoid digital
currents flowing under analog circuitry, which could occur if a
noisy digital chip is placed on the left half of the board shown in
Figure 76c. If possible, avoid large discontinuities in the ground
plane(s) (such as those formed by a long trace on the same
layer), because they force return signals to travel a longer path.
In addition, make all connections to the ground plane directly,
with little or no trace separating the pin from its via to ground.
When connecting fast logic signals (rise/fall time < 5 ns) to any
of the ADuC7019/7020/7021/7022/7024/7025/7026/7027’s
digital inputs, add a series resistor to each relevant line to keep
rise and fall times longer than 5 ns at the ADuC7019/7020/
7021/7022/7024/7025/7026/7027 input pins. A value of 100 Ω
or 200 Ω is usually sufficient enough to prevent high speed
signals from coupling capacitively into the part and affecting
the accuracy of ADC conversions.
CLOCK OSCILLATOR
The clock source for the ADuC7019/7020/7021/7022/
7024/7025/7026/7027 can be generated by the internal PLL or
by an external clock input. To use the internal PLL, connect a
32.768 kHz parallel resonant crystal between XCLKI and
XCLKO, and connect a capacitor from each pin to ground as
shown Figure 77. This crystal allows the PLL to lock correctly to
give a frequency of 41.78 MHz. If no external crystal is present,
the internal oscillator is used to give a frequency of 41.78 MHz
±
3% typically.
0
ADuC7026
TO
INTERNAL
PLL
12pF
45
XCLKI
32.768kHz
12pF
44
XCLKO
Figure 77. External Parallel Resonant Crystal Connections
To use an external source clock input instead of the PLL (see
Figure 78), Bit 1 and Bit 0 of PLLCON must be modified.The
external clock uses P0.7 and XCLK.
0
ADuC7026
TO
FREQUENCY
DIVIDER
XCLKO
XCLKI
XCLK
EXTERNAL
CLOCK
SOURCE
Figure 78. Connecting an External Clock Source
Using an external clock source, the ADuC7019/7020/7021/
7022/7024/7025/7026/7027’s specified operational clock speed
range is 50 kHz to 44 MHz
±
1% to ensure correct operation of
the analog peripherals and Flash/EE.
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