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| 型號： | ADUuC7027BSTZ62-RL |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Precision Analog Microcontroller 12-bit Analog I/O, ARM7TDMI MCU |
| 中文描述： | 精密模擬微控制器的12位模擬I / O，ARM7TDMI的微控制器 |
| 文件頁數(shù)： | 56/92頁 |
| 文件大?。?/td> | 850K |
| 代理商： | ADUUC7027BSTZ62-RL |
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ADuC7019/20/21/22/24/25/26/27
The advantage of double update mode is that lower harmonic
voltages can be produced by the PWM process and faster
control bandwidths are possible. However, for a given PWM
switching frequency, the PWMSYNC pulses occur at twice the
rate in the double update mode. Because new duty cycle values
must be computed in each PWMSYNC interrupt service
routine, there is a larger computational burden on the ARM
core in double update mode.
Rev. A | Page 56 of 92
PWM Duty Cycles (PWMCH0, PWMCH1,
PWMCH2 MMRs)
The duty cycles of the six PWM output signals on Pin PWM0
H
to Pin PWM2
L
are controlled by the three, 16-bit read/write
duty cycle registers, PWMCH0, PWMCH1, and PWMCH2.
The duty cycle registers are programmed in integer counts of
the fundamental time unit,
t
CORE
. They define the desired on-
time of the high-side PWM signal produced by the three-phase
timing unit over half the PWM period. The switching signals
produced by the three-phase timing unit are also adjusted to
incorporate the programmed dead time value in the
PWMDAT1 register. The three-phase timing unit produces
active low signals so that a low level corresponds to a command
to turn on the associated power device.
Figure 57 shows a typical pair of PWM outputs (in this case, 0H
and 0L) from the timing unit in single update mode. All
illustrated time values indicate the integer value in the
associated register and can be converted to time by simply
multiplying by the fundamental time increment,
t
CORE
. Note that
the switching patterns are perfectly symmetrical about the
midpoint of the switching period in this mode because the same
values of PWMCH0, PWMDAT0, and PWMDAT1 are used to
define the signals in both half cycles of the period.
Figure 57 also demonstrates how the programmed duty cycles
are adjusted to incorporate the desired dead time into the
resulting pair of PWM signals. Clearly, the dead time is incor-
porated by moving the switching instants of both PWM signals
(0H and 0L) away from the instant set by the PWMCH0 register.
0
–PWMDAT0/2
0H
0L
PWMSYNC
PWMSTA (0)
PWMDAT0
+PWMDAT0/2
–PWMDAT0/2
0
0
PWMDAT0
PWMDAT2+1
PWMCH0
2 × PWMDAT1
2 × PWMDAT1
PWMCH0
Figure 57. Typical PWM Outputs of Three-Phase Timing Unit
in Single Update Mode
Both switching edges are moved by an equal amount
(
PWMDAT1
×
t
CORE
) to preserve the symmetrical output
patterns.
Also shown is the PWMSYNC pulse and Bit 0 of the PWMSTA
register, which indicates whether operation is in the first or
second half cycle of the PWM period.
The resulting on-times of the PWM signals over the full PWM
period (two half periods) produced by the timing unit can be
written as follows:
On the high side
T
0HH
=
PWMDAT0
+ 2(
PWMCH0
PWMDAT1
) ×
t
CORE
T
0HL
=
PWMDAT0
2(
PWMCH0
PWMDAT1
) ×
t
CORE
and the corresponding duty cycles (
d
)
d
0H
=
T
0HH
/
T
S
= + (
PWMCH0
PWMDAT1
)/
PWMDAT0
and on the low side
T
0LH
=
PWMDAT0
2(
PWMCH0
+
PWMDAT1
)
×
t
CORE
T
0LL
=
PWMDAT0
+ 2
(PWMCH0
+
PWMDAT1
)
×
t
CORE
and the corresponding duty cycles (
d
)
d
OL
=
T
0LH
/
T
S
= (
PWMCH0
+
PWMDAT1
)/
PWMDAT0
The minimum permissible
T
0H
and
T
0L
values are zero,
corresponding to a 0% duty cycle. In a similar fashion, the
maximum value is
T
S
, corresponding to a 100% duty cycle.
Figure 58 shows the output signals from the timing unit for
operation in double update mode. It illustrates a general case
where the switching frequency, dead time, and duty cycle are all
changed in the second half of the PWM period. Of course, the
same value for any or all of these quantities can be used in both
halves of the PWM cycle. However, there is no guarantee that
symmetrical PWM signals are produced by the timing unit in
double update mode. Figure 58 also shows that the dead time
inserted into the PWM signals are done so in the same way as
demonstrated in single update mode.
0
–PWMDAT0
1
/2
0H
0L
PWMSYNC
PWMSTA (0)
PWMDAT0
1
+PWMDAT0
1
/2
–PWMDAT0
2
/2
+PWMDAT0
2
/2
PWMCH0
2
PWMCH0
1
2 × PWMDAT1
2
2 × PWMDAT1
1
PWMDAT2
2
+1
PWMDAT2
1
+1
0
0
PWMDAT0
2
Figure 58. Typical PWM Outputs of the Three-Phase Timing Unit
in Double Update Mode
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