參數(shù)資料
型號(hào)： ADUuC7027BSTZ62-RL
廠商： Analog Devices, Inc.
英文描述： Precision Analog Microcontroller 12-bit Analog I/O, ARM7TDMI MCU
中文描述： 精密模擬微控制器的12位模擬I / O，ARM7TDMI的微控制器
文件頁(yè)數(shù)： 59/92頁(yè)
文件大小： 850K
代理商： ADUUC7027BSTZ62-RL
ADuC7019/20/21/22/24/25/26/27
PWM MMRs Interface
The PWM block is controlled via the MMRs described in this
section.
Rev. A | Page 59 of 92
PWMCON Register
Name
PWMCON
Address
0xFFFFFC00
Default Value
0x0000
Access
R/W
PWMCON is a control register that enables the PWM and
chooses the update rate.
Table 35. PWMCON MMR Bit Descriptions
Bit
Name
Description
7:5
Reserved.
4
PWM_SYNCSEL
External Sync Select.
Set
to use external
sync.
Cleared
to use internal sync.
3
PWM_EXTSYNC
External Sync Select.
Set
to select
external synchronous sync signal.
Cleared
for asynchronous sync signal.
2
PWMDBL
Double Update Mode.
Set
to 1 by user
to enable double update mode.
Cleared
to 0 by the user to enable
single update mode.
1
PWM_SYNC_EN
PWM Synchronization Enable.
Set
by
user to enable synchronization.
Cleared
by user to disable synchronization.
0
PWMEN
PWM Enable Bit.
Set
to 1 by the user
to enable the PWM.
Cleared
to 0 by
the user to disable the PWM. Also
cleared automatically with PWMTRIP.
PWMSTA Register
Name
Address
PWMSTA
0xFFFFFC04
Default Value
0x0000
Access
R/W
PWMSTA reflects the status of the PWM.
Table 36. PWMSTA MMR Bit Descriptions
Bit
Name
15:10
9
PWMSYNCINT
8
PWMTRIPINT
3
PWMTRIP
2:1
0
PWMPHASE
Description
Reserved.
PWM Sync Interrupt Bit.
PWM Trip Interrupt Bit.
Raw Signal from the PWM
TRIP
Pin.
Reserved.
PWM Phase Bit.
Set
to 1 by the Micro-
Converter when the timer is counting
down (1
st
half).
Cleared
to 0 by the
MicroConverter when the timer is
counting up (2
nd
half).
PWMCFG Register
Name
PWMCFG
Address
0xFFFFFC10
Default Value
0x0000
Access
R/W
PWMCFG is a gate chopping register.
Table 37. PWMCFG MMR Bit Descriptions
Bit
Name
15:10
9
CHOPLO
8
CHOPHI
7:0
GDCLK
Description
Reserved.
Low-side gate chopping enable bit.
High-side gate chopping enable bit.
PWM gate chopping period (unsigned).
PWMEN Register
Name
PWMEN
Address
0xFFFFFC20
Default Value
0x0000
Access
R/W
PWMEN allows enabling channel outputs and crossover. See its
bit definitions in Table 38.
Table 38. PWMEN MMR Bit Descriptions
Bit
Name
Description
8
0H0L_XOVR
Channel 0 Output Crossover Enable Bit.
Set
to 1 by user to enable Channel 0 output
crossover.
Cleared
to 0 by user to disable
Channel 0 output crossover.
7
1H1L_XOVR
Channel 1 Output Crossover Enable Bit.
Set
to 1 by user to enable Channel 1 output
crossover.
Cleared
to 0 by user to disable
Channel 1 output crossover.
6
2H2L_XOVR
Channel 2 Output Crossover Enable Bit.
Set
to 1 by user to enable Channel 2 output
crossover.
Cleared
to 0 by user to disable
Channel 2 output crossover.
5
0L_EN
0L Output Enable Bit.
Set
to 1 by user to
disable the 0L output of the PWM.
Cleared
to 0 by user to enable the 0L output of the
PWM.
4
0H_EN
0H Output Enable Bit.
Set
to 1 by user to
disable the 0H output of the PWM.
Cleared
to 0 by user to enable the 0H output of the
PWM.
3
1L_EN
1L Output Enable Bit.
Set
to 1 by user to
disable the 1L output of the PWM.
Cleared
to 0 by user to enable the 1L output of the
PWM.
2
1H_EN
1H Output Enable Bit.
Set
to 1 by user to
disable the 1H output of the PWM.
Cleared
to 0 by user to enable the 1H output of the
PWM.
1
2L_EN
2L Output Enable Bit.
Set
to 1 by user to
disable the 2L output of the PWM.
Cleared
to 0 by user to enable the 2L output of the
PWM.
0
2H_EN
2H Output Enable Bit.
Set
to 1 by user to
disable the 2H output of the PWM.
Cleared
to 0 by user to enable the 2H output of the
PWM.
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