參數(shù)資料
型號： ADUuC7027BSTZ62-RL
廠商： Analog Devices, Inc.
英文描述： Precision Analog Microcontroller 12-bit Analog I/O, ARM7TDMI MCU
中文描述： 精密模擬微控制器的12位模擬I / O，ARM7TDMI的微控制器
文件頁數(shù)： 71/92頁
文件大小： 850K
代理商： ADUUC7027BSTZ62-RL
ADuC7019/20/21/22/24/25/26/27
Table 63. I2C0FSTA MMR Bit Descriptions
Bit
Value
Description
15:0
Reserved.
9
Master Transmit FIFO Flush.
Set
by the user to
flush the master Tx FIFO.
Cleared
automatically
once the master Tx FIFO is flushed. This bit also
flushes the slave receive FIFO.
8
Slave Transmit FIFO Flush.
Set
by the user to
flush the slave Tx FIFO.
Cleared
automatically
once the slave Tx FIFO is flushed.
7:6
Master Rx FIFO Status Bits.
00
FIFO Empty.
01
Byte Written to FIFO.
10
1 Byte in FIFO.
11
FIFO Full.
5:4
Master Tx FIFO Status Bits.
00
FIFO Empty.
01
Byte Written to FIFO.
10
1 Byte in FIFO.
11
FIFO Full.
3:2
Slave Rx FIFO Status Bits.
00
FIFO Empty.
01
Byte Written to FIFO.
10
1 Byte in FIFO.
11
FIFO Full.
1:0
Slave Tx FIFO Status Bits.
00
FIFO Empty.
01
Byte Written to FIFO.
10
1 Byte in FIFO.
11
FIFO Full.
PROGRAMMABLE LOGIC ARRAY (PLA)
Every ADuC7019/7020/7021/7022/7024/7025/7026/7027
integrates a fully programmable logic array (PLA), which
consists of two independent but interconnected PLA blocks.
Each block consists of eight PLA elements, which gives each
part a total of 16 PLA elements.
Rev. A | Page 71 of 92
Each PLA element contains a two-input look-up table that can
be configured to generate any logic output function based on
two inputs and a flip-flop. This is represented in Figure 62.
0
4
2
0
1
3
A
B
LOOK-UP
TABLE
Figure 62. PLA Element
In total, 30 GPIO pins are available on each ADuC7019/7020/
7021/7022/7024/7025/7026/7027 for the PLA. These include 16
input pins and 14 output pins, which need to be configured in
the GPxCON register as PLA pins before using the PLA. Note
that the comparator output is also included as one of the 16
input pins.
The PLA is configured via a set of user MMRs. The output(s) of
the PLA can be routed to the internal interrupt system, to the
CONV
START
signal of the ADC, to a MMR, or to any of the 16
PLA output pins.
The two blocks can be interconnected as follows:
Output of Element 15 (Block 1) can be fed back to Input 0 of
Mux 0 of Element 0 (Block 0)
Output of Element 7 (Block 0) can be fed back to the Input 0
of Mux 0 of Element 8 (Block 1)
Table 64. Element Input/Output
PLA Block 0
Element
Input
Output
0
P1.0
P1.7
1
P1.1
P0.4
2
P1.2
P0.5
3
P1.3
P0.6
4
P1.4
P0.7
5
P1.5
P2.0
6
P1.6
P2.1
7
P0.0
P2.2
PLA MMRs Interface
The PLA peripheral interface consists of the 22 MMRs
described in this section.
PLA Block 1
Input
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
Element
8
9
10
11
12
13
14
15
Output
P4.0
P4.1
P4.2
P4.3
P4.4
P4.5
P4.6
P4.7
PLAELMx Registers
Name
PLAELM0
PLAELM1
PLAELM2
PLAELM3
PLAELM4
PLAELM5
PLAELM6
PLAELM7
PLAELM8
PLAELM9
PLAELM10
PLAELM11
PLAELM12
PLAELM13
PLAELM14
PLAELM15
Address
0xFFFF0B00
0xFFFF0B04
0xFFFF0B08
0xFFFF0B0C
0xFFFF0B10
0xFFFF0B14
0xFFFF0B18
0xFFFF0B1C
0xFFFF0B20
0xFFFF0B24
0xFFFF0B28
0xFFFF0B2C
0xFFFF0B30
0xFFFF0B34
0xFFFF0B38
0xFFFF0B3C
Default Value
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
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