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參數(shù)資料
| 型號： | ADUuC7027BSTZ62-RL |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Precision Analog Microcontroller 12-bit Analog I/O, ARM7TDMI MCU |
| 中文描述： | 精密模擬微控制器的12位模擬I / O，ARM7TDMI的微控制器 |
| 文件頁數(shù)： | 38/92頁 |
| 文件大?。?/td> | 850K |
| 代理商： | ADUUC7027BSTZ62-RL |
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ADuC7019/20/21/22/24/25/26/27
Rev. A | Page 38 of 92
0
O
VOLTAGE INPUT (V
IN
+ – V
IN
–)
0 1111 1111 1110
0 1111 1111 1100
0 1111 1111 1010
0 0000 0000 0010
0 0000 0000 0000
1 1111 1111 1110
1 0000 0000 0100
1 0000 0000 0010
1 0000 0000 0000
–V
REF
+ 1LSB
+V
REF
– 1LSB
0LSB
1LSB =
2 × V
REF
4096
SIGN
BIT
Figure 38. ADC Transfer Function in Differential Mode
TYPICAL OPERATION
Once configured via the ADC control and channel selection
registers, the ADC converts the analog input and provides a
12-bit result in the ADC data register.
The top 4 bits are the sign bits. The 12-bit result is placed from
Bit 16 to Bit 27 as shown in Figure 39. Again, it should be noted
that in fully differential mode, the result is represented in twos
complement format, and in pseudo differential and single-
ended modes, the result is represented in straight binary format.
0
SIGN BITS
12-BIT ADC RESULT
31
27
16 15
0
Figure 39. ADC Result Format
The same format is used in DAC×DAT, simplifying the software.
Current Consumption
The ADC in standby mode, that is, powered up but not converting,
typically consumes 640 μA. The internal reference adds 140 μA.
During conversion, the extra current is 0.3 μA multiplied by the
sampling frequency (in kHz). Figure 31 shows the current
consumption versus the sampling frequency of the ADC.
Timing
Figure 40 gives details of the ADC timing. Users have control on
the ADC clock speed and on the number of acquisition clocks
in the ADCCON MMR. By default, the acquisition time is eight
clocks and the clock divider is two. The number of extra clocks
(such as bit trial or write) is set to 19, which gives a sampling
rate of 774 kSPS. For conversion on temperature sensor, the
ADC acquisition time is automatically set to 16 clocks and the
ADC clock divider is set to 32.
0
ADC CLOCK
ACQ
BIT TRIAL
DATA
ADCSTA = 0
ADCSTA = 1
ADC INTERRUPT
WRITE
CONV
START
ADC
BUSY
ADCDAT
Figure 40. ADC Timing
ADuC7019
The ADuC7019 is identical to the ADuC7020 except for one
buffered ADC channel, ADC3, and it has only three DACs. The
output buffer of the fourth DAC is internally connected to the
ADC3 channel as shown in Figure 41.
0
1MSPS
12-BIT ADC
12-BIT
DAC
MUX
ADC3
ADC15
DAC3
ADuC7019
Figure 41. ADC3 Buffered Input
Note that the DAC3 output pin must be connected to a 10 nF
capacitor to AGND. This channel should be used to measure dc
voltages only. ADC calibration might be necessary on this
channel.
MMRS INTERFACE
The ADC is controlled and configured via the eight MMRs
described in this section.
ADCCON Register
Name
ADCCON
Address
0xFFFF0500
Default Value
0x0600
Access
R/W
ADCCON is an ADC control register that allows the
programmer to enable the ADC peripheral, select the mode
of operation of the ADC (either in single-ended mode, pseudo
differential mode, or fully differential mode), and select the
conversion type. This MMR is described in Table 14.
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