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參數(shù)資料
| 型號： | ADUuC7027BSTZ62-RL |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Precision Analog Microcontroller 12-bit Analog I/O, ARM7TDMI MCU |
| 中文描述： | 精密模擬微控制器的12位模擬I / O，ARM7TDMI的微控制器 |
| 文件頁數(shù)： | 51/92頁 |
| 文件大?。?/td> | 850K |
| 代理商： | ADUUC7027BSTZ62-RL |
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ADuC7019/20/21/22/24/25/26/27
OSCILLATOR AND PLL—POWER CONTROL
Clocking System
Each ADuC7019/7020/7021/7022/7024/7025/7026/7027
integrates a 32.768 kHz
±
3% oscillator, a clock divider, and a
PLL. The PLL locks onto a multiple (1275) of the internal
oscillator or an external 32.768 kHz crystal to provide a stable
41.78 MHz clock for the system referred to as UCLK. To allow
power saving, the core can operate at this frequency, or at
binary submultiples of it. The actual core operating frequency,
UCLK/2
CD
, is refered to as HCLK. The default core clock is the
PLL clock divided by 8 (CD = 3) or 5.22 MHz. The core clock
frequency can also come from an external clock on the ECLK
pin as described in Figure 55. The core clock can be outputted
on the ECLK pin when using an internal oscillator or external
crystal.
Rev. A | Page 51 of 92
0
*32.768kHz ±3%
AT POWER UP
41.78MHz
OCLK
32.768kHz
WTIMER
INT. 32kHz*
OCRYSTAL
TIMER
MDCLK
HCLK
PLL
CORE
I
2
C
UCLK
ANALOG
PERIPHERALS
/2
CD
CD
XCLKO
XCLKI
P0.7/XCLK
P0.7/ECLK
Figure 55. Clocking System
The selection of the clock source is in the PLLCON register. By
default, the part uses the internal oscillator feeding the PLL.
External Crystal Selection
To switch to external crystal, clear the OSEL bit in the
PLLCON MMR (see Table 32). In noisy environments, noise
might couple to the external crystal pins and PLL could lose
lock momentarily. A PLL interrupt is provided in the interrupt
controller. The core clock is halted immediately and this
interrupt is only serviced once the lock has been restored.
In case of crystal loss, the watchdog timer should be used.
During initialization, a test on the RSTSTA can determine
if the reset came from the watchdog timer.
External Clock Selection
To switch to an external clock on P0.7, configure P0.7 in
Mode 1 and MDCLK bits to 11. External clock can be up
to 44 MHz providing the tolerance is 1%.
Power Control System
A choice of operating modes is available on the ADuC7019/
7020/7021/7022/7024/7025/7026/7027.
Table 30 describes what part is powered on in the different
modes and indicates the power-up time. Table 31 gives some
typical values of the total current consumption (analog + digital
supply currents) in the different modes depending on the clock
divider bits. The ADC is turned off. Note that these values also
include current consumption of the regulator and other parts
on the test board on which these values are measured.
Table 30. Operating Modes
Mode
Core
Active
X
Pause
Nap
Sleep
Stop
Peripherals
X
X
PLL
X
X
X
XTAL/T2/T3
X
X
X
X
IRQ0 to IRQ3
X
X
X
X
X
Start-up/Power-on Time
130 ms at CD = 0
24 ns at CD = 0; 3 μs at CD = 7
24 ns at CD = 0; 3 μs at CD = 7
1.58 ms
1.7 ms
Table 31. Typical Current Consumption at 25°C
PC[2-0]
Mode
000
Active
001
Pause
010
Nap
011
Sleep
100
Stop
CD = 0
33.1
22.7
3.8
0.4
0.4
CD = 1
21.2
13.3
3.8
0.4
0.4
CD = 2
13.8
8.5
3.8
0.4
0.4
CD = 3
10
6.1
3.8
0.4
0.4
CD = 4
8.1
4.9
3.8
0.4
0.4
CD = 5
7.2
4.3
3.8
0.4
0.4
CD = 6
6.7
4
3.8
0.4
0.4
CD = 7
6.45
3.85
3.8
0.4
0.4
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