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參數(shù)資料
| 型號(hào)： | ADUuC7027BSTZ62-RL |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Precision Analog Microcontroller 12-bit Analog I/O, ARM7TDMI MCU |
| 中文描述： | 精密模擬微控制器的12位模擬I / O，ARM7TDMI的微控制器 |
| 文件頁數(shù)： | 33/92頁 |
| 文件大小： | 850K |
| 代理商： | ADUUC7027BSTZ62-RL |
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ADuC7019/20/21/22/24/25/26/27
MEMORY ORGANIZATION
The ADuC7019/7020/7021/7022/7024/7025/7026/7027
incorporate two separate blocks of memory: 8 kB of SRAM and
64 kB of on-chip Flash/EE memory. Sixty-two kilobytes of on-
chip Flash/EE memory is available to the user, and the
remaining 2 kB are reserved for the factory configured boot
page. These two blocks are mapped as shown in Figure 33.
Rev. A | Page 33 of 92
0
MMRs
0xFFFFFFFF
0xFFFF0000
RESERVED
EXTERNAL MEMORY REGION 3
0x40000FFFF
0x40000000
RESERVED
EXTERNAL MEMORY REGION 2
0x30000FFFF
0x30000000
RESERVED
EXTERNAL MEMORY REGION 1
0x20000FFFF
0x20000000
RESERVED
EXTERNAL MEMORY REGION 0
0x10000FFFF
0x10000000
RESERVED
FLASH/EE
0x0008FFFF
0x00080000
RESERVED
SRAM
REMAPPABLE MEMORY SPACE
(FLASH/EE OR SRAM)
0x00011FFF
0x00010000
0x0000FFFF
0x00000000
Figure 33. Physical Memory Map
Note that by default, after a reset, the Flash/EE memory is
mirrored at address 0×00000000. It is possible to remap the
SRAM at address 0×00000000 by clearing Bit 0 of the REMAP
MMR. This remap function is described in more detail in the
Flash/EE Memory section.
MEMORY ACCESS
The ARM7 core sees memory as a linear array of 2
32
byte
location where the different blocks of memory are mapped as
outlined in Figure 33.
The ADuC7019/7020/7021/7022/7024/7025/7026/7027
memory organizations are configured in little endian format,
which means that the least significant byte is located in the
lowest byte address, and the most significant byte is in the
highest byte address.
0
BIT 31
BY.
.
.
A
6
2
BY.
.
.
B
7
3
BY.
.
.
9
5
1
BY.
.
.
8
4
0
BIT 0
32 BITS
0xFFFFFFFF
0x00000004
0x00000000
Figure 34. Little Endian Format
FLASH/EE MEMORY
The total 64 kB of Flash/EE memory is organized as 32 k ×
16 bits (31 k × 16 bits is user space and 1 k × 16 bits is reserved
for the on-chip kernel). The page size of this Flash/EE memory
is 512 bytes.
Sixty-two kilobytes of Flash/EE memory are available to the
user as code and nonvolatile data memory. There is no
distinction between data and program as ARM code shares the
same space. The real width of the Flash/EE memory is 16 bits,
which means that in ARM mode (32-bit instruction), two
accesses to the Flash/EE are necessary for each instruction
fetch. It is therefore recommended to use thumb mode when
executing from Flash/EE memory for optimum access speed.
The maximum access speed for the Flash/EE memory is
41.78 MHz in thumb mode and 20.89 MHz in full ARM mode.
More details about Flash/EE access time are outlined later in the
Execution Time from SRAM and Flash/EE section of this data
sheet.
SRAM
Eight kilobytes of SRAM are available to the user, organized as
2 k × 32 bits, that is, two words. ARM code can run directly
from SRAM at 41.78 MHz, given that the SRAM array is
configured as a 32-bit wide memory array. More details about
SRAM access time are outlined later in the Execution Time
from SRAM and Flash/EE section of this datasheet.
MEMORY MAPPED REGISTERS
The memory mapped register (MMR) space is mapped into the
upper two pages of the memory array, and accessed by indirect
addressing through the ARM7 banked registers.
The MMR space provides an interface between the CPU and
all on-chip peripherals. All registers, except the core registers,
reside in the MMR area. All shaded locations shown in
Figure 35 are unoccupied or reserved locations, and should
not be accessed by user software. Table 13 shows the full MMR
memory map.
The access time for reading from or writing to an MMR
depends on the advanced microcontroller bus architecture
(AMBA) bus used to access the peripheral. The processor has
two AMBA busses: advanced high performance bus (AHB)
used for system modules, and advanced peripheral bus (APB)
used for lower performance peripheral. Access to the AHB is
one cycle, and access to the APB is two cycles. All peripherals
on the ADuC7019/7020/7021/7022/7024/7025/7026/7027 are
on the APB except the Flash/EE memory, the GPIOs, and the
PWM.
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