參數(shù)資料
型號(hào): ADUuC7027BSTZ62-RL
廠商: Analog Devices, Inc.
英文描述: Precision Analog Microcontroller 12-bit Analog I/O, ARM7TDMI MCU
中文描述: 精密模擬微控制器的12位模擬I / O,ARM7TDMI的微控制器
文件頁(yè)數(shù): 47/92頁(yè)
文件大?。?/td> 850K
代理商: ADUUC7027BSTZ62-RL
ADuC7019/20/21/22/24/25/26/27
Reset Operation
There are four kinds of reset: external, power-on, watchdog
expiation, and software force. The RSTSTA register indicates
the source of the last reset, and RSTCLR allows clearing the
RSTSTA register. These registers can be used during a reset
exception service routine to identify the source of the reset.
If RSTSTA is null, the reset is external.
Rev. A | Page 47 of 92
REMAP Register
Name
REMAP
Address
0xFFFF0220
Default Value
0xXX
1
Access
R/W
1
Depends on model.
Table 24. REMAP MMR Bit Designations
Bit
Name
Description
4
Read-Only Bit. Indicates the size of the
Flash/EE memory available. If this bit is set,
only 32 kB of Flash/EE memory is available.
3
Read-Only Bit. Indicates the size of the SRAM
memory available. If this bit is set, only 4 kB of
SRAM is available.
2:1
Reserved.
0
Remap
Remap Bit.
Set
by user to remap the SRAM to
address 0x00000000.
Cleared
automatically
after reset to remap the Flash/EE memory to
address 0x00000000.
RSTSTA Register
Name
RSTSTA
Address
0xFFFF0230
Default Value
0x01
Access
R/W
Table 25. RSTSTA MMR Bit Designations
Bit
Description
7:3
Reserved.
2
Software Reset.
Set
by user to force a software reset.
Cleared
by setting the corresponding bit in RSTCLR.
1
Watchdog Timeout.
Set
automatically when a
watchdog timeout occurs.
Cleared
by setting the
corresponding bit in RSTCLR.
0
Power-On Reset.
Set
automatically when a power-on
reset occurs.
Cleared
by setting the corresponding bit in
RSTCLR.
RSTCLR Register
Name
RSTCLR
Address
0xFFFF0234
Default Value
0x00
Access
R/W
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