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| 型號： | ADUuC7027BSTZ62-RL |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Precision Analog Microcontroller 12-bit Analog I/O, ARM7TDMI MCU |
| 中文描述： | 精密模擬微控制器的12位模擬I / O，ARM7TDMI的微控制器 |
| 文件頁數(shù)： | 65/92頁 |
| 文件大?。?/td> | 850K |
| 代理商： | ADUUC7027BSTZ62-RL |
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ADuC7019/20/21/22/24/25/26/27
Network Addressable UART Mode
This mode connects the MicroConverter to a 256-node serial
network, either as a hardware single-master or via software in a
multimaster network. Bit 7 of COMIEN1 (ENAM bit) must be set
to enable UART in network addressable mode. Note that there is
no parity check in this mode; the parity bit is used for address.
Rev. A | Page 65 of 92
Network Addressable UART Register Definitions
Four additional registers, COMSCR, COMIEN1, COMIID1, and
COMADR are only used in network addressable UART mode.
COMSCR is an 8-bit scratch register used for temporary
storage. In network address mode, the least significant bit of the
scratch register is the transmitted network address control bit.
If set to 1, the device is transmitting an address. If cleared to 0,
the device is transmitting data.
COMIEN1 Register
Name
COMIEN1
Address
0xFFFF0720
Default Value
0x04
Access
R/W
COMIEN1 is an 8-bit network enable register.
Table 55. COMIEN1 MMR Bit Descriptions
Bit
Name
Description
7
ENAM
Network Address Mode Enable Bit.
Set
by user
to enable network address mode.
Cleared
by
user to disable network address mode.
6
E9BT
9-Bit Transmit Enable Bit.
Set
by user to enable
9-bit transmit. ENAM must be set.
Cleared
by
user to disable 9-bit transmit.
5
E9BR
9-Bit Receive Enable Bit.
Set
by user to enable
9-bit receive. ENAM must be set.
Cleared
by
user to disable 9-bit receive.
4
ENI
Network Interrupt Enable Bit.
3
E9BD
Word Length.
Set
for 9-bit data. E9BT has to be
cleared.
Cleared
for 8-bit data.
2
ETD
Transmitter Pin Driver Enable Bit.
Set
by user to
enable SOUT pin as an output in slave mode or
multimaster mode.
Cleared
by user; SOUT is
three-state.
1
NABP
Network Address Bit. Interrupt polarity bit.
0
NAB
Network Address Bit.
Set
by user to transmit the
slave’s address.
Cleared
by user to transmit data.
COMIID1 Register
Name
Address
COMIID1
0xFFFF0724
Default Value
0x01
Access
R
COMIID1 is an 8-bit network interrupt register. Bit 7 to Bit 4
are reserved (see Table 56).
Table 56. COMIID1 MMR Bit Descriptions
Bit 3:1
Status
Bits
NINT
Priority
000
1
110
0
2
Bit 0
Definition
No interrupt
Matching
network address
Address
transmitted,
buffer empty
Receive line
status interrupt
Receive buffer
full interrupt
Transmit buffer
empty interrupt
Clearing
Operation
Read COMRX
101
0
3
Write data to
COMTX or
read COMIID0
Read
COMSTA0
Read COMRX
011
0
1
010
0
2
001
0
3
Write data to
COMTX or
read COMIID0
Read COMSTA1
register
000
0
4
Modem status
interrupt
COMADR Register
Name
COMADR
Address
0xFFFF0728
Default Value
0xAA
Access
R/W
COMADR is an 8-bit, read/write network address register that
holds the address that the network addressable UART checks
for. Upon receiving this address, the device interrupts the
processor and/or sets the appropriate status bit in COMIID1.
SERIAL PERIPHERAL INTERFACE
The ADuC7019/7020/7021/7022/7024/7025/7026/7027 integrate
a complete hardware serial peripheral interface (SPI) on-chip. SPI
is an industry standard, synchronous serial interface that allows
eight bits of data to be synchronously transmitted and simultane-
ously received, that is, full duplex up to a maximum bit rate of
3.48 Mb as shown in Table 57. The SPI interface is not
operational with core clock divider bits (CD bits) POWCON[2:0]
= 6 or 7 in master mode.
The SPI port can be configured for master or slave operation
and typically consists of four pins: MISO, MOSI, SCL, and CS.
MISO (Master In, Slave Out) Pin
The MISO pin is configured as an input line in master mode
and an output line in slave mode. The MISO line on the master
(data in) should be connected to the MISO line in the slave
device (data out). The data is transferred as byte wide (8-bit)
serial data, MSB first.
MOSI (Master Out, Slave In) Pin
The MOSI pin is configured as an output line in master mode
and an input line in slave mode. The MOSI line on the master
(data out) should be connected to the MOSI line in the slave
device (data in). The data is transferred as byte wide (8-bit)
serial data, MSB first.
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