參數(shù)資料
型號(hào)： GT-48004A
廠商： Galileo Technology Services, LLC
英文描述： Four Port Switched Fast Ethernet Controller(四端口、交換式快速以太網(wǎng)控制器)
中文描述： 四端口交換式快速以太網(wǎng)控制器（四端口，交換式快速以太網(wǎng)控制器）
文件頁(yè)數(shù)： 11/106頁(yè)
文件大小： 953K
代理商： GT-48004A
GT-48004A Four Port Switched Fast Ethernet Controller
N:\Marketing\Docs\Archive\48004A\DATASHEET\Rev 1.0\484ads10.fm
Revision 1.0
12
IRdy*
I/O
Initiator Ready: Indicates the bus master’s ability to complete the current data
phase of the transaction. A data phase is completed on any clock when both
TRdy* and IRdy* are asserted. Wait cycles are inserted until both IRdy* and
TRdy* are asserted together.
AD[31:0]
I/O
Address/Data: 32-bit multiplexed PCI address and data lines. During the first
clock of the transaction, AD[31:0] contains a physical byte address (32 bits).
During subsequent clock cycles, AD[31:0] contains data.
CBE[3:0]*
I/O
Bus Command/Byte Enable: During the address phase of the PCI transac-
tion, CBE[3:0]* provide the Bus Command. During the data phase, CBE[3:0]*
provide Byte Enables, which determine which bytes carry valid data.
Int0/1*
O
Interrupt Request Line0/1 : Int* is asserted byand FEU in the GT-48004A
when one (or more) of the bits in the Interrupt Cause register(s) are set. These
outputs use an open-collector driver and can be wired-ORed in most applica-
tions.
DRAM Interfaces: ‘A’ interface is for Fast Ethernet Unit 0; ‘B’ is for Fast Ethernet Unit 1
ADData[31:0]
I/O
DRAM Data for Fast Ethernet Unit 0: 32-bit EDO DRAM data bus. These sig-
nals connect directly to the data input/output pins of the DRAM devices.
BDData[31:0]
I/O
DRAM Data for Fast Ethernet Unit 1: same as above.
ADAddr[8:0]
I/O
DRAM Multiplexed Address Bus for Fast Ethernet Unit 0: In normal opera-
tion, ADAddr[8:0] contain the DRAM multiplexed row/column address. During
RESET, these multiplexed pins are sampled by the GT-48004A to indicate the
Device Number and the DRAM Parameters (see RESET Configuration Section
20.) Values are determined by connecting pull-up/pull-down resistors. The
Device Number and the DRAM Size are read by the CPU from the Status reg-
ister.
BDAddr[8:0]
I/O
DRAM Multiplexed Address Bus for Fast Ethernet Unit 1: same as above.
ARAS[1:0]*
O
Row Address Strobes for Fast Ethernet Unit 0: DRAM row address strobes.
ARAS[0]* is used for Bank 0. ARAS[1]* is used for Bank 1.
BRAS[1:0]*
O
Row Address Strobes for Fast Ethernet Unit 1: same as above.
ACAS*
O
Column Address Strobe for Fast Ethernet Unit 0: DRAM column address
strobe. The GT-48004A always accesses 32-bit values and does not require a
separate ACAS* for each byte.
BCAS*
O
Column Address Strobe for Fast Ethernet Unit 1: same as above.
AWE*
O
Write Enable for Fast Ethernet Unit 0: DRAM write enable.
BWE*
O
Write Enable for Fast Ethernet Unit 1: same as above.
Media Independent Interface (MII)
TxEn[3:0]
O
Transmit Enable: Active HIGH. This output indicates that the packet is being
transmitted. TxEn is synchronous to TxClk.
TxClk[3:0]
I
Transmit Clock: Provides the timing reference for the transfer of TxEn, TxD
signals. TxClk frequency is one fourth of the data rate (25 MHz for 100Mbps,
2.5 MHz for 10Mbps). TxClk nominal frequency should match the nominal fre-
quency of RxClk for the same port.
TxD0[3:0]
O
Transmit Data 0: Outputs the Port0 Transmit Data. Synchronous to TxClk[0].
TxD1[3:0]
O
Transmit Data 1: Outputs the Port1 Transmit Data. Synchronous to TxClk[1].
TxD2[3:0]
O
Transmit Data 2: Outputs the Port2 Transmit Data. Synchronous to TxClk[2].
Sy m b ol
Ty p e
De s c ri pti o n
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