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參數(shù)資料
| 型號： | GT-48004A |
| 廠商： | Galileo Technology Services, LLC |
| 英文描述： | Four Port Switched Fast Ethernet Controller(四端口、交換式快速以太網(wǎng)控制器) |
| 中文描述： | 四端口交換式快速以太網(wǎng)控制器（四端口，交換式快速以太網(wǎng)控制器） |
| 文件頁數(shù)： | 78/106頁 |
| 文件大小： | 953K |
| 代理商： | GT-48004A |
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GT-48004A Four Port Switched Fast Ethernet Controller
73
Revision 1.0
N:\Marketing\Docs\Archive\48004A\DATASHEET\Rev 1.0\484ads10.fm
19.
Interrupts
The GT-48004A signals interrupts to a management CPU via the PCI INTA# pin. Interrupts are maskable through the
Interrupt Mask register and the interrupt source is determined through the Interrupt Cause register. The Interrupt Mask
register defaults to masking all interrupts. A ‘0’ in the appropriate bit means that particular interrupt will be masked. A ‘1’
in the appropriate bit means that particular interrupt will not be masked. The default is that all interrupts are masked.
Interrupts are cleared by writing ‘0’ to the corresponding bit in the Interrupt Cause register. Writing ‘1’ to a bit in the
Cause register has no effect.
NOTE: There is an Interrupt Cause and Mask register in each FEU. The interrupts requested by each FEU are ORed
before being brought out to the package pin.
20.
RESET Configuration
The GT-48004A uses several pins as configuration inputs to set certain parameters following a RESET. The definition
of the configuration pins changes immediately after RESET to their usual function.
20.1
Configuration Pins
Configuration pins must be pulled up or down externally at RESET to select the desired operational parameter. The
recommended value of the pull-up/down resistors is 4.7K ohms. Table 34 shows the configuration pins for the GT-
48004A.
20.2
Configuration Input Timings
The configuration inputs have two timing requirements:
setup/hold time to clock (as any synchronous input)
setup of at least 10 clock cycles before RESET de-assertion (rising edge).
You can guarantee these parameters by using resistors to strap the configuration pins and delaying RESET de-asser-
Table 34: RESET Pin Strapping Options
Pin
Co nf igur at ion Fu nct i on
A/BDAddr[4:0]
Device Number: Each FEU must have a different device number.
A/BDAddr[5]
DRAM Size for FEU
0-
1-
2Mbyte
1Mbyte
A/BDAddr[6]
Half/Full Duplex Mode for Port 0/2
0-
1-
Half Duplex
Full Duplex
A/BDAddr[7]
Half/Full Duplex Mode for Port 1/3
0-
1-
Half Duplex
Full Duplex
A/BDAddr[8]
DRAM Type for each FEU
0-
1-
Reserved
EDO
LEDMode*
LED Mode
0-
1-
LEDMode 0
LEDMode 1
ForceLinkPass*
Force Link Pass
0-
1-
Read Link Status from the PHY via SMI
Force Link Status to “l(fā)ink is up”
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