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參數(shù)資料
| 型號： | GT-48004A |
| 廠商： | Galileo Technology Services, LLC |
| 英文描述： | Four Port Switched Fast Ethernet Controller(四端口、交換式快速以太網(wǎng)控制器) |
| 中文描述： | 四端口交換式快速以太網(wǎng)控制器（四端口，交換式快速以太網(wǎng)控制器） |
| 文件頁數(shù)： | 29/106頁 |
| 文件大?。?/td> | 953K |
| 代理商： | GT-48004A |
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GT-48004A Four Port Switched Fast Ethernet Controller
29
Revision 1.0
N:\Marketing\Docs\Archive\48004A\DATASHEET\Rev 1.0\484ads10.fm
CRC generator enhances system performance by implementing the CPU intensive packet CRC calculation in hard-
ware. Note that CRC generation is not required for packets transferred between GalNet devices, since the CRC is
already appended to these packets.
CRC generation for CPU generated packets is enabled through the EnCRC bit in the Global Control register (bit 29). In
addition, the CPU must set the GenCRC bit in the END_OF_PACKET (Section 11.3.12) message sent to the GT-
48004A at the completion of forwarding the packet.
7.7
Tx Watchdog Timer
The GT-48004A includes a transmit watchdog timer for each transmit queue. For 100Mbps operation, the default value
of the timer is 63msec; the range is between 10.5 to 168msec. For 10Mbps operation, the default value of the timer is
630msec and the range is between 105msec to 1680msec. The timer measures the time between the transmission of
two consecutive outgoing packets. When the timer expires, the GT-48004A clears the appropriate used blocks and
sends an interrupt to the CPU via Int*.
The transmit watchdog timer prevents transmission problems on one port from blocking traffic to other ports. In man-
aged systems, the timers also provide a mechanism to notify the CPU of a possible system problem.
The Tx Watchdog Timer can be externally disabled by holding the DisWD* pin LOW. The default is to leave the Tx
Watchdog Timer enabled (DisWD* HIGH.)
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