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參數(shù)資料
| 型號(hào)： | GT-48004A |
| 廠商： | Galileo Technology Services, LLC |
| 英文描述： | Four Port Switched Fast Ethernet Controller(四端口、交換式快速以太網(wǎng)控制器) |
| 中文描述： | 四端口交換式快速以太網(wǎng)控制器（四端口，交換式快速以太網(wǎng)控制器） |
| 文件頁數(shù)： | 31/106頁 |
| 文件大?。?/td> | 953K |
| 代理商： | GT-48004A |
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GT-48004A Four Port Switched Fast Ethernet Controller
N:\Marketing\Docs\Archive\48004A\DATASHEET\Rev 1.0\484ads10.fm
Revision 1.0
30
8.
Device Table Operation
The GalNet Architecture supports a maximum of 32 devices per system. Each device needs to know of the existence of
all other GalNet devices in the system in order to communicate information and packet data. The Device Table is a 32-
bit register that uses a single bit for each possible Device Number to indicate its presence/absence in the system.
8.1
Automatic Device Table Initialization
Upon RESET, each FEU in each GT-48004A in the system sets all of its Device Table bits to ‘1’. This is essentially a
“guess” by the FEU that
all Device Numbers are in use. In a system with any PCI device that is NOT a GalNet device
(CPU, graphics card, etc.), it recommended that the CPU initialize the device table before the GalNet device is enabled
(or before packet transmission starts).
Specific Device Table bits are cleared, and the corresponding Device Numbers are logically eliminated from the sys-
tem, by:
The receipt of a PCI Master Abort when the GT-48004A attempts to access the corresponding Device Number
Management CPU programming
Device Table “cleaning” is handled automatically by each device upon receipt of the first unknown packet following a
RESET. This process discovers all other GalNet devices in the system without processor intervention:
1.
The GT-48004A receives the first good packet from any Ethernet port and places it in the buffer area in DRAM.
2.
Since the Address Table is cleared (immediately following RESET) the packet must be forwarded to all ports,
including those located on other GalNet devices.
3.
The GT-48004A attempts to allocate a buffer in all 31 possible additional GalNet devices in the system. This is
done by issuing 31 BUFFER_REQUEST messages- one to every possible device in the system.
4.
Each BUFFER_REQUEST message that fails due to a PCI Master Abort results in the corresponding Device Num-
ber bit being cleared in the Device Table. A PCI Master Abort only occurs when there is no target device at the
requested address (i.e. the target device doesn’t exist.)
NOTE: Each FEU in a GT-48004A performs the above process separately.
8.2
Manual Device Table Initialization
Alternatively, the CPU can notify each FEU within the GT-48004A of the existence of the GalNet devices. This is done
by setting the by setting bit 2 in the global control register (DevTabMod.) In this mode, the CPU is responsible for noti-
fying the GT-48004A of the existence of all GT-4800x devices in the system. The CPU does this by writing the appro-
priate values to each device table.
“Manual” mode must be used when there are multiple PCI buses in the system separated via PCI-to-PCI bridges.
8.3
Programming Device Numbers
The Device Number for each FEU in the GT-48004A is set after RESET by the values on the xDAddr[4:0] pins. The
device number can be changed by writing the new device number to [26:22] of the DRAM/Internal Register Base
Address Register at 0x010 (each FEU is addresses separately.) Typically, once the number of a device has been
changed, the device table of all devices in the system will also need to be updated.
NOTE: Each FEU in a GT-48004A must have a different device number.
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