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參數(shù)資料
| 型號： | GT-48004A |
| 廠商： | Galileo Technology Services, LLC |
| 英文描述： | Four Port Switched Fast Ethernet Controller(四端口、交換式快速以太網(wǎng)控制器) |
| 中文描述： | 四端口交換式快速以太網(wǎng)控制器（四端口，交換式快速以太網(wǎng)控制器） |
| 文件頁數(shù)： | 23/106頁 |
| 文件大?。?/td> | 953K |
| 代理商： | GT-48004A |
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GT-48004A Four Port Switched Fast Ethernet Controller
23
Revision 1.0
N:\Marketing\Docs\Archive\48004A\DATASHEET\Rev 1.0\484ads10.fm
Table 3: GT-48004A DRAM Address Mapping per FEU
6.1
Rx Buffer Threshold Programming
The number of receive buffers allocated to each port of the GT-48004A is controlled by the RxBufThr field in the Rx
Buffer Threshold register and the DisBufThr* pin. The default value is 80 buffers per port for 1MB DRAM and 140 buff-
ers per port for 2MB DRAM. If the buffer threshold is disabled (by clearing the BufThrEn bit in the Global Control regis-
ter or if the DisBufThr* pin is held LOW) the GT-48004A dynamically allocates the buffers to the 2 ethernet ports in
each FEU and the PCI bus port. In other words, there are no limits on each buffers’ allocation. The Rx Buffer Threshold
value can be used to tune performance during development. See Table 4 for Rx Buffer Threshold settings.
If a received packet overflows the Rx buffer allowance, then that packet will be discarded and the Dropped Packets
counter will be incremented. The overflow of the Rx buffer allowance is also indicated by the “Receive Buffer Full” LED
in the Serial and Parallel LED Interfaces.
Table 4: Setting the Rx Buffer Threshold
Mem o ry
D esc ri pti o n
1M b y te
2Mbyt e
Rx Buffers
320 Buffers for 1Mbyte
1008 Buffers for 2 Mbyte
0x00000 - 0x7cfff
0x00000 - 0x17cfff
PCI Tx Descriptor
0x7d000 - 0x08efff
0x17d000 - 0x18efff
PCI Rx Descriptor
0x8f000 - 0x9afff
0x18f000 - 0x19afff
Reserved
4KBytes
0x9b000 - 0x09bfff
0x19b000 - 0x19bfff
Tx Descriptor
0x09c000 - 0x09ffff
0x19c000 - 0x19ffff
Address Table
0xa0000 - 0xfffff
0x1a0000 - 0x1fffff
D i sB uf Thr * P i n
Bu fT h r En Bi t
R esu lt
HIGH
1
Receive Buffer Size is limited to the
value of RxBufThr
HIGH
0
Dynamic Receive Buffer Allocation
LOW
1
Dynamic Receive Buffer Allocation
LOW
0
Dynamic Receive Buffer Allocation
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