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參數(shù)資料
| 型號(hào)： | GT-48004A |
| 廠商： | Galileo Technology Services, LLC |
| 英文描述： | Four Port Switched Fast Ethernet Controller(四端口、交換式快速以太網(wǎng)控制器) |
| 中文描述： | 四端口交換式快速以太網(wǎng)控制器（四端口，交換式快速以太網(wǎng)控制器） |
| 文件頁(yè)數(shù)： | 22/106頁(yè) |
| 文件大小： | 953K |
| 代理商： | GT-48004A |
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GT-48004A Four Port Switched Fast Ethernet Controller
N:\Marketing\Docs\Archive\48004A\DATASHEET\Rev 1.0\484ads10.fm
Revision 1.0
22
6.
GT-48004A
Buffers and Queues
The GT-48004A incorporates three transmit queues for the 2 Ethernet ports and the PCI bus port, and one common
receive buffer area in each FEU. The receive buffers as well as the transmit queues are located in the DRAM along
with the Address Table. DRAM address mapping for each FEU in the GT-48004A is shown in Table 3. The GT-48004A
data structure components are the following:
Receive Buffer - A common Receive Buffer area for all ports. The buffer is divided into 320 or 1008 blocks
(depending on the DRAM size) of 1.5KBytes (1536 bytes) each. Each block contains the entire packet.
Rx Empty List - A list of 320 or 1008 bits. Each bit contains the status of its appropriate receive block in the
DRAM (empty or occupied).
Tx Descriptors - A set of 3 transmit descriptor rings. Each ring contains 1024 descriptors. The descriptor size
is one 32-bit word and contains the Block Address divided by 0x600 (1.5K), the byte count and the packet type
(Multicast or Unicast).
Read/Write Pointers - 3 pairs of pointers to the transmit descriptors.
Figure 5: GT-48004A Buffers and Queues
Read Pointer
Write Pointer
21
Byte Count Blk Addr
10 9
0
Frame #0
Frame #1
Frame #2
Receive Buffer (for all ports and PCI)
Tx Descriptors: 1024 X 3
Rx Empty List
DRAM
GT-48004A
M/U
20
Frame #n
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