參數(shù)資料
型號： GT-48004A
廠商： Galileo Technology Services, LLC
英文描述： Four Port Switched Fast Ethernet Controller(四端口、交換式快速以太網(wǎng)控制器)
中文描述： 四端口交換式快速以太網(wǎng)控制器（四端口，交換式快速以太網(wǎng)控制器）
文件頁數(shù)： 88/106頁
文件大?。?/td> 953K
代理商： GT-48004A
GT-48004A Four Port Switched Fast Ethernet Controller
N:\Marketing\Docs\Archive\48004A\DATASHEET\Rev 1.0\484ads10.fm
Revision 1.0
82
Status, Offset: 0x14002c (Read-Only)
CPU and Sniffer Numbers, Offset: 0x140030
Bi ts
Fi e l d Na m e
Fun cti o n
In iti a l Va l u e
4:0
DevNum
Device Number.
Indicates the GT-48004A number chosen by the
designer.
DAddr[4:0] at RESET
5
DRAMSize
DRAM Size.
Indicates the DRAM size.
0- 2Mbyte
1- 1Mbyte
DAddr[5] at RESET
6
Port0Par
Port0 Partition.
This bit indicates the port 0 Partition status.
0 - No Partition (Normal mode)
1 - Partition
0x0
7
Port0LTF
Port0 Link Test Fail.
This bit indicates the port 0 Link Test status.
0 - Link Test Pass
1 - Link Test Fail
0x0
8
Port1Par
Port1 Partition.
This bit indicates the port 1 Partition status.
0 - No Partition (Normal mode)
1 - Partition
0x0
9
Port1LTF
Port1 Link Test Fail.
This bit indicates the port 1 Link Test status.
0 - Link Test Pass
1 - Link Test Fail
0x0
Bi ts
Fi e l d Na m e
Fun cti o n
In iti a l Va l u e
4:0
SnifDevNum
Sniffer Device Number.
These bits specify the Sniffer Device Number chosen
by the designer. The same value should be pro-
grammed to all GT-48004A/GT-48001A devices shar-
ing the same PCI bus.
0x0 (bit 4 is MSB)
7:5
SnifPortNum
Sniffer Port Number.
These bits specify the Sniffer Port Number chosen by
the designer. The same value should be programmed
to all GT-48004A/GT-48001A devices sharing the
same PCI bus.
0x0 (bit 7 is MSB)
12:8
CPUDevNum
CPU Device Number.
These bits specify the Device Number of the CPU as
chosen by the designer. This number must not be the
same as any other GalNet device is the system. The
same value should be programmed to all GT-48004A/
GT-48001A devices sharing the same PCI bus. The
corresponding bit for the CPUDevNum value should
be set in the Device table (offset 0x40) for all GT-
48004A/GT-48001A devices sharing the same PCI
bus.
0x0 (bit 12 is MSB)
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