參數(shù)資料
型號(hào)： GT-48004A
廠商： Galileo Technology Services, LLC
英文描述： Four Port Switched Fast Ethernet Controller(四端口、交換式快速以太網(wǎng)控制器)
中文描述： 四端口交換式快速以太網(wǎng)控制器（四端口，交換式快速以太網(wǎng)控制器）
文件頁(yè)數(shù)： 99/106頁(yè)
文件大?。?/td> 953K
代理商： GT-48004A
GT-48004A Four Port Switched Fast Ethernet Controller
N:\Marketing\Docs\Archive\48004A\DATASHEET\Rev 1.0\484ads10.fm
Revision 1.0
92
Status and Command, PCI Offset: 0x004
Bi ts
Fi e l d Na m e
Fun cti o n
In iti a l Va l u e
1
MemEn
Memory Enable.
Controls the GT-48004A’s response to memory
accesses.
0 - Disable, the GT-48004A will ignore all memory
accesses on the PCI bus.
1 - Enable, the GT-48004A will respond to memory
accesses on the PCI bus.
0x1
2
MasEn
Master Enable.
Controls the GT-48004A’s ability to act as a master on
the PCI bus.
0 - Disable
1 - Enable
0x1
4
MemWrInv
Memory Write and Invalidate.
Controls the GT-48004A’s ability to generate Memory
Write and Invalidate commands on the PCI bus.
0 - Disable
1 - Enable
0x0
5
Reserved
Reserved.
Read only.
0x0
6
ParEn
Parity Enable.
Controls the GT-48004A’s ability to respond to parity
errors on the PCI.
0 - Disable
1 - Enable
0x0
8
SysErrEn
System Error Enable.
Controls the GT-48004A’s ability to assert the SErr*
pin.
0 - Disable
1 - Enable
0x0
22:9
Reserve
Reserved.
Read only.
0x0
23
TarFastBB
Target Fast Back-to-Back.
This indicates that the GT-48004A is capable of
accepting Fast Back-to-Back transactions on the PCI
bus. Read-only bit.
0x1
24
DataParDet
Data Parity Detected.
This bit is set by the GT-48004A when it detects a
Data Parity Error during a master operation. This bit is
cleared by writing ‘1’ to it.
0x0
26:25
DevSelTim
Device Select Timing.
These bits indicate the GT-48004A‘s DevSel* timing.
The GT-48004A’s DevSel* timing is always set at
medium (01), as defined in the PCI specification.
Read only.
0x1
28
TarAbort
Target Abort.
This bit is set upon Target Abort. This bit is cleared by
writing ‘1’ to it.
0x0
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