參數(shù)資料
型號(hào)： GT-48004A
廠商： Galileo Technology Services, LLC
英文描述： Four Port Switched Fast Ethernet Controller(四端口、交換式快速以太網(wǎng)控制器)
中文描述： 四端口交換式快速以太網(wǎng)控制器（四端口，交換式快速以太網(wǎng)控制器）
文件頁(yè)數(shù)： 17/106頁(yè)
文件大?。?/td> 953K
代理商： GT-48004A
GT-48004A Four Port Switched Fast Ethernet Controller
N:\Marketing\Docs\Archive\48004A\DATASHEET\Rev 1.0\484ads10.fm
Revision 1.0
18
4.
Operational Overview
The GalNet Architecture Family of switching devices has been defined as an extensible, scalable architecture for the
switching of packetized data. The GalNet Architecture Family currently supports Ethernet (GT-48001A), Fast Ethernet
(GT-48002A and GT-48004A), and 100VG-AnyLAN (GT-48003.)
All GalNet Architecture Family devices act as distributed intelligent agents within a switching system. Each GalNet
device makes switching decisions independent of other devices in the system, and can communicate information
regarding the network to all other agents. This distributed processing approach is a significant performance improve-
ment over switching architectures that rely on centralized switching “engines” or single-point address recognition
devices. Unlike centralized resource approaches, GalNet designs can actually add packet processing capability as
additional ports are added.
The GalNet Architecture Family uses a “store-and-forward” switching approach. Store-and-forward was chosen for the
following reasons:
Store-and-forward switches allow switching between differing speed media (e.g. 10BaseX and 100BaseX.)
Such switches require the large elastic buffers that are provided by the EDO DRAM arrays.
Store-and-forward switches improve overall network performance by acting as a “network cache”, effectively
buffering packets during periods of heavy congestion.
Store-and-forward switches prevent the forwarding of corrupted packets by analyzing the frame check
sequence (FCS) before forwarding to the destination port.
A typical unmanaged GalNet Architecture system is extremely simple to implement as shown in Figure 1 on page 8. No
CPU is needed as each GalNet device is intelligent and capable of sharing network information and packet data auton-
omously. A CPU may be added to provide network management capability.
4.1
Enabling/Disabling the GT-48004A
Ports of the GT-48004A can be enabled and disabled depending on the combination of:
An external hardware pin, EnDev* (LOW - device enabled, HIGH - device disabled)
EnableDevice, bit 27 of the Global Control Register (‘0’ - device status based on EnDev*, ‘1’ - device enabled)
PortEn, bit 0 of each Port Control Register, (‘0’ - port disabled, ‘1’ - port enabled)
When a port is disabled, no packets will be received or transmitted from the serial ports or the PCI bus. Even though
ports are disabled, another PCI master can read from and write to the GT-48004A’s registers. See Table 1 for enabling
or disabling ports of the GT-48004A.
Table 1: Enabling/Disabling Ports of the GT-48004A
4.2
Basic Operation
The basic operation of the GT-48004A is quite simple. The GT-48004A receives incoming packets from the Fast Ether-
net wire, searches in the Address Table for the Destination MAC Address and then forwards the packet to the appropri-
ate port. The destination port can be either be local (one of the GT-48004A’s ports) or in a different GT-48004A device
that resides on the same PCI bus. If the destination address is not found, the GT-48004A treats the packet as a multi-
E n D ev*
Pi n
E n ab leD evi ce
Bi t
Po rt En
Bi t
Por t St atu s
LOW
0
Disabled
LOW
0
1
Enabled
LOW
1
0
Disabled
LOW
1
Enabled
HIGH
0
Disabled
HIGH
0
1
Disabled
HIGH
1
0
Disabled
HIGH
1
Enabled
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