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GT-48004A Four Port Switched Fast Ethernet Controller
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13.
Fast Ethernet Interfaces
Each FEU in the GT-48004A interfaces directly to two MII (Media Independent Interface) ports (4 ports total) which are
compliant with the IEEE standard (please see 802.3u Fast Ethernet standard for detailed interface information and tim-
ing parameters). Each MII port has the following characteristics:
Capable of supporting both 10 Mbps and 100 Mbps data rates in half or full duplex modes
Data and delimiters are synchronous to clock references
Provides independent 4-bit wide transmit and receive paths
Uses TTL signal levels
Provides a simple management interface (common to all ports)
Capable of driving a limited length of shielded cable
The GT-48004A incorporates all the required digital circuitry to interface to 100BaseTX, 100BaseT4, and 100BaseFX.
Two Fast Ethernet ports are integrated in the GT-48004A and only a small amount of external logic is needed to imple-
ment the standard physical interfaces.
13.1
10/100 MII Compatible Interface
The GT-48004A MAC allows it to be connected to a 10Mbps or 100Mbps network. The GT-48004A interfaces to an
IEEE 802.3 10/100 Mbps MII compatible PHY device. The data path consists of a separate nibble-wide stream for both
transmit and receive activities. The GT-48004A can switch automatically between 10 or 100 Mbps operation depending
on the speed of the network. Data transfers are clocked by the 25 MHz transmit and receive clocks in 100 Mbps oper-
ation, or by 2.5 MHz transmit and receive clocks in 10 Mbps operation. The clock inputs are driven by the PHY, which
controls the clock rate based on auto-negotiation.
13.2
Media Access Control (MAC)
The GT-48004A MAC performs all of the functions of the 802.3 protocol such as frame formatting, frame stripping, col-
lision handling, deferral to link traffic, etc. The GT-48004A ensures the any outgoing packet complies with the 802.3
specification in terms of preamble structure. The GT-48004A transmits 56 preamble bits before Start of Frame Delim-
iter (SFD). The GT-48004A operates in half-duplex or full-duplex modes. In half-duplex mode, the GT-48004A checks
that there is no competitor for the network bus before transmission. In addition to listening for a clear line before trans-
mitting, the GT-48004A handles collisions in a pre-determined way. If two nodes attempt to transmit at the same time,
the signals collide and the data on the line is garbled. The GT-48004A listens while it is transmitting, and it can detect a
collision. If a collision is detected, the GT-48004A transmits a ‘JAM’ pattern and then delays its re-transmission for a
random time period determined by the backoff algorithm. In full-duplex mode, the GT-48004A transmits unconditionally.
13.3
Auto-negotiation
13.3.1 Disabled
When EnAutoNeg* is HIGH, auto-negotiation is disabled both ports and each port can be selected to be in half- or full-
duplex mode independently. Following RESET the port duplex mode is set by the state sampled on DAddr[6] for Port 0
and DAddr[7] for Port 1 (for each FEU). This value can be overridden in each port’s Port Control register. The speed
that each port operates in (10Mbps or 100Mbps) is determined by the frequency of TxClk[x] and RxClk[x] generated by
the PHY. When the port is operating at 10Mbps, the PHY generates a 2.5MHz clock for both TxClk and RxClk. When
the port is operating at 100Mbps, the PHY generates a 25MHz clock for both TxClk and RxClk.
13.3.2 Enabled
When EnAutoNeg* is LOW, auto-negotiation is enabled for both ports and the GT-48004A decodes the duplex mode
for each port from the values of the Auto-Negotiation Advertisement register and the Auto-Negotiation Link Partner
Ability registers at the end of the Auto-Negotiation process. (Note: The auto-negotiation feature on the 48002A is used
ONLY to tell the 48002A-P-2 the duplex that each port is operating in. The SPEED (10/100) of each port is determined
ONLY by RxClk and TxClk.) Once the duplex mode is resolved, the GT-48004A updates the port control registers with
that duplex mode. The GT-48004A will continuously perform the following operations for each port (PHY addresses 1