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參數(shù)資料
| 型號： | GT-48004A |
| 廠商： | Galileo Technology Services, LLC |
| 英文描述： | Four Port Switched Fast Ethernet Controller(四端口、交換式快速以太網(wǎng)控制器) |
| 中文描述： | 四端口交換式快速以太網(wǎng)控制器（四端口，交換式快速以太網(wǎng)控制器） |
| 文件頁數(shù)： | 25/106頁 |
| 文件大?。?/td> | 953K |
| 代理商： | GT-48004A |
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GT-48004A Four Port Switched Fast Ethernet Controller
25
Revision 1.0
N:\Marketing\Docs\Archive\48004A\DATASHEET\Rev 1.0\484ads10.fm
source GT-48004A also clears the appropriate bit in its Empty List.
6.
Some packet information included in the END_OF_PACKET message is written to the appropriate transmit
descriptor in the target device. This information includes the Byte Count and the Receive Buffer address which is
pointed to by the Write Pointer.
7.
The Write Pointer of the outgoing port’s transmit descriptor is incremented. The target GalNet device transmits
whenever the Write Pointer is not equal to the Read Pointer.
8.
At the end of the packet transmit process, the target GalNet device increments the Read Pointer and clears the
appropriate bit in the Empty List.
7.3
Forwarding a Multicast Packet
The GT-48004A forwards Multicast packets to all local ports and devices using the same mechanism as described for
Unicast packets. The GT-48004A has the ability to forward multicast packets to a management CPU for intervention
routing, if desired.
7.3.1
Local Ports
For local ports in the same device, the packet is queued to all transmit ports except for the port which the packet
arrived and the packet is transferred with the same procedure outlined in Section 7.1 to each port.
7.3.2
Between GalNet Devices or FEUs
Forwarding multicast packets to other GalNet devices is handled differently depending if a CPU is disabled or enabled
in the system or not.
7.3.2.1
CPU Disabled
Systems which do not utilize a CPU (bit 10 of the Global Control Register, 0x140028, is not set) will automatically for-
ward multicast packets to all of the local ports and devices with the following procedure:
1.
The incoming packet is fed to the Rx FIFO and is transferred to an empty block in the Receive Buffer area of
DRAM.
2.
In parallel, an address recognition cycle is performed for the SA. The DA marks this packet as a multicast packet.
At the end of a good packet transfer, packet is forwarded to all of the local ports according to Section 7.3.1. This
multicast packet is also forwarded to the other GalNet devices in the system with the same procedure as forward-
ing a unicast packet from one device to another. This procedure is outlined in Section 7.2. There is a single, sepa-
rate, multicast packet transfer from the source GT-48004A to each of the GalNet devices in the system. Bit 21 of
Data 0 of the BUFFER_REQUEST message (Section 11.2.2) will be set to indicate this is a multicast packet.
7.3.2.2
CPU Enabled
Systems which utilize a CPU (bit 10 of the Global Control Register, 0x140028, is set), will
always have multicast pack-
ets forwarded to the CPU. This allows the CPU to intervene, if necessary, and redirect or update the multicast packet
before forwarding. Control of forwarding multicast packets to all of the ports is set by bit 22 of the Global Control Regis-
ter. The default setting is to forward all multicast packets to all of the ports in the system as well as the CPU. If this bit is
set, multicast packets will go
only to the CPU.
Assuming bit 22 is not set and all multicast packets are forwarded to the CPU as well as all of the ports, the procedure
for handling multicast packets is as follows:
1.
The incoming packet is fed to the Rx FIFO and is transferred to an empty block in the Receive Buffer area of
DRAM.
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