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參數(shù)資料
| 型號： | GT-48004A |
| 廠商： | Galileo Technology Services, LLC |
| 英文描述： | Four Port Switched Fast Ethernet Controller(四端口、交換式快速以太網(wǎng)控制器) |
| 中文描述： | 四端口交換式快速以太網(wǎng)控制器（四端口，交換式快速以太網(wǎng)控制器） |
| 文件頁數(shù)： | 91/106頁 |
| 文件大?。?/td> | 953K |
| 代理商： | GT-48004A |
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GT-48004A Four Port Switched Fast Ethernet Controller
85
Revision 1.0
N:\Marketing\Docs\Archive\48004A\DATASHEET\Rev 1.0\484ads10.fm
Rx Buffers Threshold, Offset: 0x040224
Bi ts
Fi e l d Na m e
Fun cti o n
In iti a l Va l u e
3:0
TxWatTim
Tx Watchdog Timer.
For 100 Mbps operation, the default value of the timer
is 63msec and the range is between 10.5mSec and
168msec, in 10.5 ms steps. For 10 Mbps operation,
the default value of the timer is 630msec and the
range is between 105ms to 1680ms, in 105 ms steps.
Valid values: 1 to F hex.
Value should be written in hexadecimal format.
0x6 (63 ms @
100Mbps; 630 ms @
10 Mbps)
8:4
-
Reserved.
0x04
12:9
RxBufThr
Rx Buffer Threshold.
These bits determine the threshold of the receive buff-
ers. Meaningful only when the BufThrEn bit in the Glo-
bal Control register is set. The Rx Buffer Threshold
equals to: (RxBufThr x 20 + 20), the step is 20, and
the value varies between 20 (0x0) and 320 (0xf). The
default is 80 (0x3) for 1MB DRAM and 140 (0x6) for
2MB DRAM.
Value should be written in hexadecimal format.
0x3 (80) @ 1M DRAM
0x6 (140) @ 2M
DRAM
15:13
-
Reserved. During writes to this register, bits 15:13
must be written to their default values.
0x1 @ 1M DRAM
0x3 @ 2M DRAM
18:16
PCIBufThr
PCI Buffer Threshold.
These bits determine the threshold of the PCI receive
buffers. The PCI Buffer Threshold equals to:
(PCIBufThr x 50 +100). step is 50, and the value var-
ies between100 (0x0) and 320 (0xf). The default is
150 (0x1) for 1MB DRAM and 200 (0x2) for 2MB
DRAM.
Value should be written in hexadecimal format.
0x1 (150) @ 1M
DRAM
0x2 (200) @ 2M
DRAM
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
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| GT48300-A1-BBE-C000 | 制造商:Marvell 功能描述:Marvell GT48300-A1-BBE-C000 |
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