參數(shù)資料
型號(hào)： GT-48004A
廠商： Galileo Technology Services, LLC
英文描述： Four Port Switched Fast Ethernet Controller(四端口、交換式快速以太網(wǎng)控制器)
中文描述： 四端口交換式快速以太網(wǎng)控制器（四端口，交換式快速以太網(wǎng)控制器）
文件頁(yè)數(shù)： 18/106頁(yè)
文件大?。?/td> 953K
代理商： GT-48004A
GT-48004A Four Port Switched Fast Ethernet Controller
19
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cast packet and forward the packet to all ports of all devices in the system specified to forward unknown packets.
The GT-48004A automatically learns the port number of attached network devices by examining the Source MAC
Address of all incoming packets. If the Source Address is not found in the GT-48004A’s Address Table, the device adds
it to the table (with an indication of on which port the address resides). The GT-48004A then notifies other GalNet
devices in the system of the new address via a NEW_ADDRESS message.
4.3
Address Learning
The GT-48004A can learn up to 8K unique MAC addresses. Addresses are stored in the Address Table located in
DRAM. The Address Table is managed automatically by the GT-48004A (i.e. a new address is automatically added to
the Address Table). The GT-48004A’s address learning process is outlined in Section 5.
The Address Table includes information regarding target port, aging status, static/dynamic status, and flags to force
processor intervention. The management CPU has the ability to insert, remove or modify the entries.
4.4
Packet Buffering
Incoming packets are buffered in the DRAM array. These buffers provide elastic storage for transferring data between
low-speed and high-speed segments. The packet buffers are managed automatically by the GT-48004A.
4.5
Packet Forwarding
Once an address has been learned, and the packet is buffered, it must be forwarded. The packet forwarding mecha-
nism for the GT-48004A is handled automatically based on the destination address. Optionally, the CPU can be
involved in unicast packet forwarding decisions by using
intervention mode. If a CPU is utilized for system manage-
ment functions, multicast packets will be forwarded to the CPU for forwarding decisions.
4.6
The GalNet Protocol
The GT-48004A uses a proprietary inter-chip communication protocol on the PCI bus known as the GalNet Protocol
messages.
The
protocol
consists
of
five
groups
of
messages:
NEW_ADDRESS,
BUFFER_REQUEST,
START_OF_PACKET, PACKET_TRANSFER, and END_OF_PACKET.
All GalNet messages are
write-only. For example, a GT-48004A may request a buffer location in another GalNet device
by writing a BUFFER_REQUEST message to the target device. The target device responds by writing a
START_OF_PACKET message to the requesting GT-48004A. Read transactions are strictly avoided since they tend to
stall the PCI bus, thereby wasting precious bandwidth.
4.7
Terminology
It is important to understand the basic terminology used to describe the GalNet Architecture Family before getting into
the detailed description. Table 2 explains the terms used throughout this document.
Table 2: Terminology
Te rm
De fi n i t i on
Address Table
The Address Table is a data structure in the GT-48004A’s DRAM that con-
tains all learned MAC addresses, and routing information associated with
those addresses.
Source Address
The Source Address (SA) is the MAC address from which a received
packet was sent.
Destination Address
The Destination Address (DA) is the MAC address to which a received
packet was sent.
Device Number
Each GalNet device in a system (including the CPU, if any) has a specific
Device Number. There are 32 possible Device Numbers.
Port Number
Each Ethernet port on a GalNet device has an associated port number.
The GalNet device associates Port Numbers with the MAC addresses
located on those ports.
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