參數(shù)資料
型號(hào): LR4500
廠商: LSI Corporation
英文描述: Superscalar Microprocessor(超標(biāo)量微處理器)
中文描述: 超標(biāo)量微處理器(超標(biāo)量微處理器)
文件頁數(shù): 119/172頁
文件大?。?/td> 1142K
代理商: LR4500
7-1
Chapter 7
SCbus and Local I/O
Bus Converter Module
This chapter discusses the Lbus, and describes how the LR4500
Microprocessor reference device interacts with the Lbus through the
SCLC module. The chapter contains the following sections:
Lbus Features
,” on
page 7-1
.
LR4500 as Master on the Lbus
,” on
page 7-2
.
LR4500 as Slave on the Lbus
,” on
page 7-5
.
SCbus Timeout Watchdog Timer
,” on
page 7-8
.
External Vectored Interrupt (EVInt) Support
,” on
page 7-9
.
7.1 Lbus Features
The Lbus is similar to the VLbus or 486 bus, which has a demultiplexed
32-bit address bus and a 32-bit data bus.
“Lbus Interface” on page 5-5
provides a list of Lbus signals.
There are certain differences between the Lbus and the VLbus, as shown
below:
Feature
Lbus
VLbus
I/O space
Interrupt acknowledge cycle
Support for single transactions
Support for burst transactions
HOLD/HLDA bus arbitration
Bus retry input
Uses Lbus clock, LCLKp
No
No
Yes
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
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