參數(shù)資料
型號： LR4500
廠商： LSI Corporation
英文描述： Superscalar Microprocessor(超標(biāo)量微處理器)
中文描述： 超標(biāo)量微處理器（超標(biāo)量微處理器）
文件頁數(shù)： 66/172頁
文件大?。?/td> 1142K
代理商： LR4500
4-30
Instruction Set
WB
Write Back Data Cache
Format
Syntax
WB offset(
base
)
Description
Eight words of the Data cache line addressed by
offset + GPR[base]
are written back to memory if the line is dirty. Upper bits of
offset
+ GPR[base
] are ignored.
Exceptions
None
4.3 CPU Instruction Opcode Bit Encoding
Tables
4.15
through
4.21
show the opcode bit encoding for CW4011
instructions. The following keys are referenced in the tables:
31
26 25
21 20
16 15
0
CACHE
base
WB
offset
101111
base
00100
offset
*rxf1
Operation codes marked with *rxf1 cause reserved instruction
exceptions in all current implementations and are reserved for future
versions of the architecture.
*rxf2
Operation codes marked with *rxf2 cause reserved instruction
exceptions in all current implementations and are reserved for future
versions of the architecture. *rxf2 is separated from other reserved
instructions for COPz. These are not detected as reserved instruction
codes that cause an exception on the R3000. The R4000 detects them.
*rx40
An operation code marked with *rx40 causes a reserved instruction
exception on R4000 and CW4011 processors (when in R4000 mode).
It is used as a Restore From Exception (RFE) instruction on the R3000,
LR33000, LR33300, and CW4011 in R3000 mode.
*rx64
Operation codes marked with *rx64 cause a reserved instruction
exception. They are 64-bit instructions on R4000.
*nrx
Operation codes marked with *nrx are invalid but do not cause reserved
instruction exceptions in CW4011 implementations.
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