參數(shù)資料
型號(hào)： LR4500
廠商： LSI Corporation
英文描述： Superscalar Microprocessor(超標(biāo)量微處理器)
中文描述： 超標(biāo)量微處理器（超標(biāo)量微處理器）
文件頁數(shù)： 130/172頁
文件大?。?/td> 1142K
代理商： LR4500
8-2
Cache Configuration and Maintenance
Table 8.1 Cache Size and Accessing
Select between direct-mapped and two-way set-associative caching.
To do this you program bits IE[1:0] for the I-cache and DE[1:0] for
the D-cache, as shown in
Table 8.1
. IE1 and IE0 enable I-cache Set-
1 and Set-0, respectively, and DE1 and DE0 enable D-cache Set-1
and Set-0, respectively. In the example shown in
Table 8.1
, Set-0 is
enabled for both the I-cache and the D-cache when you require
direct mapping, and Set-1 is disabled for both caches. When you
select two-way set-associative caching, both sets are enabled for
both caches. Note that when you select two-way set-associative
caching, total cache capacity is doubled, since you are using both
cache sets.
Configure the D-cache as scratchpad RAM.
Prior to configuring a set’s associativity as scratchpad RAM, you
must use cache isolation and tag test modes to program the corre-
sponding tag memory to contain the desired physical addresses.
When using isolate cache mode, stores to cache are not propagated
to external memory. To initiate isolate cache and test tags mode, you
must set bits IsC and TAG in the CCC Register, as described in
Section 3.3.1, “CCC Register,”
on
page 3-5
.
Cache Bit Settings
Configuration
IE1 or DE1 IE0orDE0
IS[1:0] or DS[1:0]
0
0
X X
1
1. The setting of these bits does not matter.
No cache
0
1
0 0
1 Kbyte direct mapped
0
1
0 1
2 Kbyte direct mapped
0
1
1 0
4 Kbyte direct mapped
0
1
1 1
8 Kbyte direct mapped
1
1
0 0
2 Kbyte two-way set-associative
1
1
0 1
4 Kbyte two-way set-associative
1
1
1 0
8 Kbyte two-way set-associative
1
1
1 1
16 Kbyte two-way set-associative
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