參數(shù)資料
型號(hào): LR4500
廠商: LSI Corporation
英文描述: Superscalar Microprocessor(超標(biāo)量微處理器)
中文描述: 超標(biāo)量微處理器(超標(biāo)量微處理器)
文件頁數(shù): 62/172頁
文件大?。?/td> 1142K
代理商: LR4500
4-26
Instruction Set
MSUBU
Multiply Subtract Unsigned
Format
Syntax
MSUBU rs, rt
Description
The contents of general register
rs
and
rt
are multiplied and both
operands are treated as 32-bit unsigned values. When the operation is
completed, the doubleword result is subtracted from special register pair
HI/LO.
No overflow exception occurs under any circumstances.
This instruction is only available when the chip has multiplier-accumulator
module hardware and MAD/MUL are set to one in the CCC register.
The instruction executes in multiple cycles, depending on the number of
significant bits in the operands. Refer to
Table 4.15
on
page 4-31
.
Operation
T:
t <- (HI || LO) - ((0||GPR[rs]) * (0||GPR[rt]))
LO <- t31..0, HI <- t
63..32
Exceptions
None
31
26 25
21 20
16 15
11 10
6
5
0
SPECIAL
rs
rt
0
0
MSUBU
000000
rs
rt
0
00000
011111
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