參數(shù)資料
型號： LR4500
廠商： LSI Corporation
英文描述： Superscalar Microprocessor(超標(biāo)量微處理器)
中文描述： 超標(biāo)量微處理器（超標(biāo)量微處理器）
文件頁數(shù)： 152/172頁
文件大小： 1142K
代理商： LR4500
9-20
ICEport
Figure 9.12 Received Bit Timing
The Rx block places in the Rx Data Register the eight data bits received
after the start bit. The first data bit received after the start bit is the LSB
(bit 0), and the eighth data bit received is the MSB (bit 7). The eight data
bits received between the start and stop bits are all true level values.
A valid HIGH stop bit received at the end of the frame sets the RxRDY
bit in the Rx Status Register. The IRXRDYp (sc_ICEINTp) output reflects
the state of the RxRDY bit, if IRXRDYp is enabled by the RxRXRDYPe
bit in the Rx Setup Register. IRXRDYp can be used as an interrupt to
ensure that the CPU reads the data received, thus avoiding overruns. If
the stop bit is LOW, the frame is ignored.
A received data byte is not placed in the Rx Data register until a valid
stop bit is received. This data byte will be available through the next data
byte (frame) receive, until the next valid stop bit refreshes the Rx Data
register. In other words, a previously received data byte is present in the
Rx Data register for at least nine bit cycles (144 ICECLKp cycles) after
a new start bit for a new frame is received.
If a previously received byte has not been read when a new byte is ready
for the Rx Data register, an overrun error occurs. When an overrun error
occurs, the ICEport sets the RxOverrun bit int he Rx Status register, and
the new frame is discarded.
If the ICEport receives an invalid stop bit, the stop bit is not recorded by
the ICEport registers, but the frame is still discarded. The ICEport will not
accept a new start bit until the previous frame has been finished by a
valid stop bit or a HIGH value on ICERXp. This ensures that the ICEport
will not indicate a runaway receive if ICERXp is continuously either HIGH
or LOW. Therefore, the ICEport will not receive a frame after reset if
ICERXp is continuously either HIGH or LOW.
ICECLKp
16 cycles
ICERXp
Start
Bit
First
Data Bit
Second
Data Bit
16 cycles
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