參數(shù)資料
型號: LR4500
廠商: LSI Corporation
英文描述: Superscalar Microprocessor(超標量微處理器)
中文描述: 超標量微處理器(超標量微處理器)
文件頁數(shù): 19/172頁
文件大?。?/td> 1142K
代理商: LR4500
CW4011 Shell
2-3
2.1.1 CW4011 Core
The CW4011 core is an encrypted Verilog RTL model that is part of
LSI Logic’s CoreWare Library. The CW4011 core is a predefined
hardmacro that contains the following basic microprocessor elements:
Instruction Scheduling Unit (ISU)
Load/Store Unit (LSU)
Arithmetic Logic Unit (ALU)
Coprocessor 0 (CP0)
Bus Interface Unit (BIU)
The CW4011 core executes all MIPS II 32-bit based instructions except
for multiply/divide instructions. These instructions are handled by the
MDU, which is part of the CW4011 shell.
For detailed information about the CW4011 core, refer to the MiniRISC
CW4011 Superscalar Microprocessor Technical Manual
2.1.2 Multiply/Divide Unit
The multiply/divide unit supports multiply-add/subtract operations as well
as multiply and divide. The multiply instruction executes in three cycles.
The multiply-add/subtract instruction is optimized to one cycle.
2.1.3 Memory Management Unit Shell
The MMU does not have a TLB. kseg0 and kseg1 are mapped to the
first 512 Mbyte space, which is the bottom of the memory space. The
kuseg and kseg2 blocks are directly mapped to the physical address
space without any change. “
Section 3.2,
on
page 3-4
, provides more
information on this subject.
2.1.4 Write Back Buffer
The CW4011 core uses this buffer when the D-cache operates in
write back mode. When a cache miss occurs and the victim entry
contains a dirty line, the dirty data is written into the Write Back Buffer
instead of the main memory. This reduces the latency of the cache refill
for missed addresses. Data in the Write Back Buffer is written into the
main memory after the refill is completed.
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