參數(shù)資料
型號(hào): LR4500
廠商: LSI Corporation
英文描述: Superscalar Microprocessor(超標(biāo)量微處理器)
中文描述: 超標(biāo)量微處理器(超標(biāo)量微處理器)
文件頁數(shù): 157/172頁
文件大?。?/td> 1142K
代理商: LR4500
Exception Inputs
10-3
Figure 10.2 Timing Requirements for the CW4011 and Lbus Clocks
10.2 Exception Inputs
Exception inputs to the LR4500 may be asynchronous. These inputs
include:
Cold reset exception input, SCRESETn
Warm reset exception input, SWRESETn
Nonmaskable interrupt exception, SNMin
External interrupt exceptions, SEXTiNTn[5:0]
The SCLC module in the LR4500 has a synchronization circuit that
synchronizes these inputs to the system clock, SCLKp. As shown in
Figure 10.3
, the synchronization circuit consists of a series of D-type
flip-flops that are clocked on the rising edge of SCLKp. The exception
inputs reset the first stage, Flip-Flop A. On the rising edge of SCLKp, the
Q output from A is passed to the D-input of Flip-Flop B. The next SCLKp
input clocks this stage, and the Q output from B is passed to the D-input
of the final stage, which outputs synchronous exception signals on the
rising edge of the third SCLKp.
Figure 10.4
shows the timing
requirements for the synchronization circuit.
SCLKp
(pin input)
SCLKp
LCLKp
LCLKp
LCLKp
LCLKp
MCLKp
(internal signal)
(pin output)
(internal signal...1/2)
(pin output...1/2)
(internal signal...1/4)
(pin output...1/4)
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