參數(shù)資料
型號(hào): LR4500
廠商: LSI Corporation
英文描述: Superscalar Microprocessor(超標(biāo)量微處理器)
中文描述: 超標(biāo)量微處理器(超標(biāo)量微處理器)
文件頁數(shù): 84/172頁
文件大?。?/td> 1142K
代理商: LR4500
5-14
Bus Interface Descriptions
DRRDYn
DRAM Ready
The DRAMC asserts DRRDYn when the current DRAM
transaction is terminated, indicating that the bus is
available. The signal remains active (LOW) until the next
transaction starts. The DRAMC outputs the signal to the
SCLC, which merges DRRDYn with its own bus ready
signal (
page 5-19
) and drives SCBRDYn, which is output
to the CW4011 shell.
Output from DRAMC to SCLC
iCiNVSn
I-cache Invalidation Strobe
Input to Shell from
SCLC
The SCLC asserts this signal to indicate that the CiNVAp
invalidation address bus is valid for I-cache and there is
a need for a snooping sequence. If the cache tag is not
coincident with higher address bits, the line is not
invalidated.
SCAp[31:0]
Address Bus Bidirectional between Shell and SCLC
Input to DRAMC
The CW4011 asserts the signals on this bus and outputs
them to the SCLC or the DRAMC. The Lbus master can
also assert SCAp[31:0] and output the address to the
CW4011 shell through the SCLC. SCAp[31:0] is the
32-bit address bus used for instruction fetch and data
read/write operations. The bus signals are valid only
when the address output enable signal, SCAoEn, is
asserted. The enable signal remains valid throughout the
operation until SCBRDYn, SCBRTYn, or SCBERRn is
asserted.
SCAoEn
Address Output Enable
Output from Shell to
DRAMC
The CW4011 asserts this signal, to indicate that the
address bus lines, SCAp[31:0], are valid. The signal
remains active throughout the bus transaction. SCAoEn
also enables SCTBSTn, SCTBEn, and SCTPWn. This
signal is never valid at the same time as SLAoEn (the
Address Output Enable signal output from the SCLC shell
to the DRAMC (
page 5-19
). When TESTMp is asserted,
SCAoEn is asserted. Other address output enable
signals must be deasserted when TESTMp is asserted.
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