參數資料
型號： LR4500
廠商： LSI Corporation
英文描述： Superscalar Microprocessor(超標量微處理器)
中文描述： 超標量微處理器（超標量微處理器）
文件頁數： 150/172頁
文件大小： 1142K
代理商： LR4500
9-18
ICEport
9.6.3 The Serial Bit Stream
The ICEport receives data on ICERXp and transmits data on ICETXp in
serial bit streams. In the Receive (Rx) block, the ICEport receives data.
When no data is being transferred, the Transmit (Tx) block holds ICETXp
idle HIGH.
Figure 9.10
shows an interpretation of the serial bit stream on the data
line. The data bytes are received in frames, with each frame consisting
of three pieces:
a start bit, always LOW
a byte of data, transmitted at a true level from LSB (bit 0) to MSB
(bit 7)
a stop bit, always HIGH
All bits in a frame are the 16 ICECLKp cycles long. The data line remains
HIGH after the stop bit when the line goes idle, until the next start bit
drives the line LOW.
Figure 9.10 Serial Bit Stream
9.6.4 ICEport Receive and Transmit
There are two ICEport serial interface blocks, specifically the receive (Rx)
and transmit (Tx) blocks. The Rx block receives the ICERXp bit stream,
and the Tx block transmits the ICETXp bit stream. Both blocks receive
the internal CPU clock (SCLKp) and the external bit rate clock
(ICECLKp). Both blocks synchronize timing between the ICECLKp and
SCLKp timing domains.
Figure 9.11
shows a block diagram of the Rx and
Tx blocks with I/O and clock signals.
0
1
2
3
4
5
6
7
Data Line
Bit Positions
Frame
Idle State
Start
Bit
Data Byte
Stop
Bit
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