參數(shù)資料
型號: LR4500
廠商: LSI Corporation
英文描述: Superscalar Microprocessor(超標(biāo)量微處理器)
中文描述: 超標(biāo)量微處理器(超標(biāo)量微處理器)
文件頁數(shù): 156/172頁
文件大?。?/td> 1142K
代理商: LR4500
10-2
Organization of Clock and Exception Signals
Table 10.1
summarizes the clock generation process.
Figure 10.2
shows
the timing requirements for the CW4011 and Lbus clocks.
Figure 10.1 LR4500 PLL Clock Circuitry
Table 10.1 Summary of LR4500 Clocks
Clock Name
Source
Frequency
Comments
SCLKp
Pin input SCLKp
DC to 100 MHz
CW4011 clock
MCLKp
SCLKp
Same as SCLKp
frequency
DRAM clock, SCLKp monitor
clock
LCLKp
SCLKp divided by 2, or
SCLKp divided by 4
1/2 or 1/4 of SCLKp
frequency
Lbus clock
LCRESETn
LCHALFn
D
Q
QN
CD
Internal LCLKp
(SCLC)
Internal SCLKp
(CW4011, DRAMC,SCLC)
SCLKp
D
Q
QN
CD
b
a
z
s
SCLKp
-pin
LCLKp
-pin
Lbus
Device
Clock
Clock Input
Driver with PLL
Output
Buffer
Internal
Clock Buffer
MCLKp
-pin
SCLKp Monitor
DRAM Clock
Output
Buffer
2:1 Multiplexer
Multiplexer input ‘b’ generates the 1/2 clock, multiplexer input ‘a(chǎn)’ generates the 1/4 clock
When LCHALFn is HIGH, it enables the input on pin ‘b’ to be output on pin ‘z’ of the multiplexer,
generating the 1/2 clock
When LCHALFn is LOW, it enables the input on pin ‘a(chǎn)’ to be output on pin ‘z’ of the multiplexer,
generating the 1/4 clock
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