參數(shù)資料
型號： LR4500
廠商： LSI Corporation
英文描述： Superscalar Microprocessor(超標量微處理器)
中文描述： 超標量微處理器（超標量微處理器）
文件頁數(shù)： 120/172頁
文件大?。?/td> 1142K
代理商： LR4500
7-2
SCbus and Local I/O Bus Converter Module
The Lbus is synchronized by the Lbus clock, LCLKp, which is derived
from the CW4011 system clock, SCLKp. The LR4500 outputs the LCLKp
to the Lbus.
The LR4500 can function as the Lbus master or the Lbus slave. If the
LR4500 is master, it starts an Lbus transaction while LHLDAp is
deasserted. If an Lbus device wants to control the Lbus and initiate a bus
transaction, it must first take ownership of the bus by issuing a bus hold
request (by asserting LHoLDp) to the LR4500. The LR4500 returns a bus
hold acknowledge signal (by asserting LHLDAp) to the Lbus device,
granting bus ownership. When this occurs, the Lbus device may initiate
Lbus transactions.
The Lbus master starts a transaction on the Lbus by asserting the
Address Strobe, (LADSn). At this time, the master must also drive valid
information on the address bus and the byte enable lines. The Lbus
master uses LRDn signal to control the direction of the data transfer. The
master must present the appropriate level on this signal at the same time
it asserts strobe signal LADSn. During a write transaction, the master
must also drive valid data on the data bus.
When the transaction has been successfully completed, the selected
slave device asserts LRDYn, indicating that the Lbus is ready for another
transaction. The master must continue to drive all signals until it samples
LRDYn. If the transaction is a read transaction, the slave device must
place valid data on the bus before it asserts LRDYn.
7.2 LR4500 as Master on the Lbus
The LR4500 is the master of the Lbus when the CW4011 accesses an
address in the Lbus area located in the physical address range
0x1100 0000 through 0xFFFF FFFF. The Lbus device must assert a data
ready or bus retry signal and input it to the LR4500 within 256 SCLKp
cycles. Otherwise, the SCbus watchdog timer terminates the SCbus
transaction by asserting a bus error signal.
Figure 7.1
shows the timing
requirements for an Lbus read transaction generated by the CW4011
core.
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LR4-550 功能描述:可復(fù)位保險絲 5.5A 20V 100A Imax RoHS:否 制造商:Bourns 電流額定值: 電阻:7.5 Ohms 最大直流電壓: 保持電流:0.1 A 安裝風格:SMD/SMT 端接類型:SMD/SMT 跳閘電流:0.6 A 引線間隔: 系列:MF-PSHT 工作溫度范圍:- 40 C to + 125 C
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