參數(shù)資料
型號: LR4500
廠商: LSI Corporation
英文描述: Superscalar Microprocessor(超標量微處理器)
中文描述: 超標量微處理器(超標量微處理器)
文件頁數(shù): 7/172頁
文件大小: 1142K
代理商: LR4500
Contents
vii
Transaction
Timing Requirements for an SCbus-to-Lbus Write
Transaction
Timing Requirements for Lbus-to-SCbus Read Transaction
Timing Requirements for Lbus-to-SCbus Write Transaction
SCbus Error Address and Error Status Register Bit Format
External Vectored Interrupt Register Bit Format
CW4011 Design with ICEport
ICEport Block Diagram
Rx Status Register
Rx Setup Register
Rx Data Register
Tx Status Register
Tx Data Register
Read Transaction
Write Transaction
Serial Bit Stream
Rx and Tx Blocks
Received Bit Timing
LR4500 PLL Clock Circuitry
Timing Requirements for the CW4011 and Lbus Clocks
Exception Inputs Synchronization Circuitry
Timing Requirements for Synchronization Circuit
AC Timing for LR4500 Inputs and Outputs
256 PQFPt Mechanical Drawing
256 PQFPt Pinouts
7-3
7.2
7-4
7-6
7-7
7-8
7-9
9-2
9-3
9-11
9-12
9-13
9-13
9-14
9-16
9-16
9-18
9-19
9-20
10-2
10-3
10-4
10-4
11-5
11-6
11-8
7.3
7.4
7.5
7.6
9.1
9.2
9.3
9.4
9.5
9.6
9.7
9.8
9.9
9.10
9.11
9.12
10.1
10.2
10.3
10.4
11.1
11.2
11.3
Tables
3.1
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
LR4500 Registers
Load and Store Instructions
Load Linked MIPS II Instructions
ALU Immediate Instructions
ALU Three-Operand Register Type Instructions
Shift Instructions
Multiply/Divide Instructions
Extended Computational Instructions
Jump Instructions
3-2
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
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