參數(shù)資料
型號(hào)： LR4500
廠商： LSI Corporation
英文描述： Superscalar Microprocessor(超標(biāo)量微處理器)
中文描述： 超標(biāo)量微處理器（超標(biāo)量微處理器）
文件頁數(shù)： 93/172頁
文件大?。?/td> 1142K
代理商： LR4500
Internal Interface
5-23
EXVApEn
EXVAp Enable
This is the enable signal for the vectored interrupt
address. The CW4011 asserts this signal to acknowledge
the address.
Output from Shell to SCLC
EXViNTn
External Vectored Input
The SCLC drives this signal. When the CW4011 shell
receives the signal, it generates an external vectored
interrupt exception.
Input to Shell from SCLC
FRCMn
Force Cache Miss (Strap Input)
This input is used for system debug. Under normal
operating conditions, you should deassert FRCMn by
strapping it HIGH. To use it for debug, you should assert
it by tying it LOW. When LOW, the signal forces a cache
miss for the I-cache and the D-cache in the CW4011
shell. The CW4011 treats this event as an access to an
uncached area. The CW4011 can then read and write all
instructions and data as uncached, regardless of the
memory segment and the MMU.
Input to Shell
SEXiNTn[5:0] External Interrupt Input Signals [5:0]
The SCLC asserts one of the SEXiNT signals to cause
the CP0 in the CW4011 core to generate an interrupt
exception. The assertion is registered in the IP field of the
CW4011 Cause Register. The SCLC should continue to
assert the signals until the exception routine has serviced
the interrupt.
Input to Shell
The CW4011 does not recognize interrupts if the interrupt
enable bit in the Status Register is not set. The CW4011
can therefore disable individual interrupt inputs by
clearing the related bits. However, the interrupt inputs are
still registered in the IP field of the Cause Register.
External Interrupt Input signals [5:0] are synchronized to
the system clock, SCLKp, in the SCLC.
The MiniRISC CW4011 Superscalar Microprocessor
Core Technical Manual provides information about the
CW4011 CP0 registers.
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